Abstract: An interface circuit for interconnecting an integrated injection logic (I.sup.2 L) portion of an integrated circuit to a linear portion of an integrated circuit. The circuit transfers both logic information and I.sup.2 L current level references from the I.sup.2 L circuitry to the linear circuitry at the relatively large voltage levels present in linear circuitry. One embodiment employs a cascode arrangement involving one transistor, two diodes and a resistor. Another embodiment utilizes the matching characteristics of a pair of transistors operating in the forward and reverse modes respectively to perform the function with only one transistor.