Patents by Inventor James Jann-Ming Wu

James Jann-Ming Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6227211
    Abstract: The poor uniformity of Interlevel Dielectric Deposition (ILD) thickness for High Aspect Ratio (HAR) contact after Chemical Mechanical Planarization (CMP) will cause serious underlayer loss due to the longer over-etching time that is required to compensate for thickness differences within the wafer. Prior Art uses 1.5K Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PETEOS) to serve as a stop layer and thus reduce underlayer loss. The present invention teaches using a non-silicon oxide containing SiN/SiON or Si3N4/SiON as a stop layer. The present invention therefore is aimed at reducing underlayer loss and thereby improving the uniformity of the underlayer thickness upon completion of the hole etching process. Concurrently, the over-etch time can be reduced to less than 10% of the time required for Prior Art contact hole etching.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: May 8, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Bao Ru Yang, Wen-Chuan Chiang, James Jann-Ming Wu