Patents by Inventor James Jen-Ho Wang

James Jen-Ho Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10685944
    Abstract: In accordance with an embodiment, sensor structure has a first, second, and third laminated structures. The second laminated structure is positioned between the first laminated structure and the third laminated structure. The first laminated structure includes a first portion of a first sensing element and the third laminated structure includes a second portion of the first sensing element. The second laminated structure includes spacer elements that can be used to adjust the sensitivity of the sensor structure.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: June 16, 2020
    Inventor: James Jen-Ho Wang
  • Publication number: 20180114784
    Abstract: In accordance with an embodiment, sensor structure has a first, second, and third laminated structures. The second laminated structure is positioned between the first laminated structure and the third laminated structure. The first laminated structure includes a first portion of a first sensing element and the third laminated structure includes a second portion of the first sensing element. The second laminated structure includes spacer elements that can be used to adjust the sensitivity of the sensor structure.
    Type: Application
    Filed: October 23, 2017
    Publication date: April 26, 2018
    Inventor: James Jen-Ho Wang
  • Patent number: 9799448
    Abstract: In accordance with an embodiment, a circuit element includes a flexible foldable substrate having portions of a first inductor formed on first and second major surfaces of the flexible substrate. In accordance with another embodiment, a first electrically conductive trace having a first terminal, a second terminal, and a first annular-shaped portion between the first terminal and the second terminal is formed on a first portion of the first major surface. A second electrically conductive trace having a first terminal, a second terminal, a first annular-shaped portion between the first terminal and the second terminal of the second electrically conductive trace, and a second annular-shaped portion between the first terminal and the second terminal of the second electrically conductive trace is formed on the second major surface. The first electrically conductive trace is coupled to the second electrically conductive trace by a thru-via.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: October 24, 2017
    Assignee: Power Gold LLC
    Inventor: James Jen-Ho Wang
  • Patent number: 9704644
    Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: July 11, 2017
    Inventor: James Jen-Ho Wang
  • Publication number: 20170186533
    Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.
    Type: Application
    Filed: November 3, 2014
    Publication date: June 29, 2017
    Inventor: James Jen-Ho Wang
  • Patent number: 9668352
    Abstract: A flexible printed circuit assembly, having a first flexible printed circuit having a first conductive layer and a device that is connected the first conductive layer; and a second flexible printed circuit having a second conductive layer, an insulating center layer, and a third conductive layer, the insulating center layer arranged in-between the second and the third conductive layers, the second conductive layer and the insulating center layer being removed to form an opening to expose an upper surface of the third conductive layer, wherein the first flexible printed circuit is arranged such that the device is accommodated inside the opening, a lower surface of the device being in thermal connection with the third conductive layer, and the first conductive layer is arranged to be in electrical connection with the second conductive layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 30, 2017
    Assignees: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., Power Gold LLC
    Inventors: James Jen-ho Wang, Jin Joo Park, Masahiko Kouchi
  • Publication number: 20160163451
    Abstract: In accordance with an embodiment, a circuit element includes a flexible foldable substrate having portions of a first inductor formed on first and second major surfaces of the flexible substrate. In accordance with another embodiment, a first electrically conductive having a first terminal, a second terminal, and a first annular-shaped portion between the first terminal and the second terminal trace is formed on a first portion of the first major surface. A second electrically conductive trace having a first terminal, a second terminal, a first annular-shaped portion between the first terminal and the second terminal of the second electrically conductive trace, and a second annular-shaped portion between the first terminal and the second terminal of the second electrically conductive trace is formed on the second major surface. The first electrically conductive trace is coupled to the second electrically conductive trace by a thru-via.
    Type: Application
    Filed: October 2, 2014
    Publication date: June 9, 2016
    Inventor: James Jen-Ho Wang
  • Publication number: 20160126010
    Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.
    Type: Application
    Filed: November 3, 2014
    Publication date: May 5, 2016
    Inventor: James Jen-Ho Wang
  • Patent number: 9282596
    Abstract: Intelligent lighting system 100 is configured to operate from an AC source 12. An array of visible light emitting diodes (LEDs) 124 responds to environmental room conditions monitored by a sensor circuit. A microcontroller 146 operates in response to sensor circuit communications to control the state of the visible light array. An internal low noise voltage source VL is derived from the waste heat product from a portion of the LED array. The low noise voltage source is used to power the sensor circuit and the microcontroller.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: March 8, 2016
    Assignee: POWER GOLD LLC
    Inventor: James Jen-Ho Wang
  • Patent number: 8998454
    Abstract: A flexible circuit assembly for accommodating a plurality of power electronic devices, including an insulating cover layer having first openings for power electronic devices, a flexible conductive layer arranged under the insulating cover layer and attached with a first adhesive to the insulating cover layer, an intermediate insulating layer arranged under the flexible conductive layer and attached with a second adhesive to the flexible conductive layer, the intermediate insulating layer having second openings, a plurality of heat-conductive elements arranged inside the second openings, a first thin heat sink layer, the heat-conductive elements arranged to be in contact with an upper surface of the thin heat sink layer and the lower surface of the islands via heat-conductive material; and a second thin heat sink layer, upper surfaces of the power electronic devices arranged to be in contact with a lower surface of the thin heat sink layer and the lower surface of the islands via heat-conductive material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 7, 2015
    Assignees: Sumitomo Electric Printed Circuits, Inc., Power Gold LLC
    Inventors: James Jen-Ho Wang, Jin Joo Park
  • Patent number: 8890287
    Abstract: A high value capacitance per unit area capacitor is fabricated on a substrate 1 by converting a portion of a primary function anti-reflecting conducting layer 36 to a high value dielectric layer 37 by partially oxidizing the conducting layer to form the dielectric layer. The resultant combination is sandwiched between two metal layer electrodes 35 and 55 to complete the capacitor structure.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: November 18, 2014
    Assignee: Power Gold LLC
    Inventor: James Jen-Ho Wang
  • Patent number: 8879276
    Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: November 4, 2014
    Assignee: Power Gold LLC
    Inventor: James Jen-Ho Wang
  • Publication number: 20140268780
    Abstract: A flexible circuit assembly for accommodating a plurality of power electronic devices, including an insulating cover layer having first openings for power electronic devices, a flexible conductive layer arranged under the insulating cover layer and attached with a first adhesive to the insulating cover layer, an intermediate insulating layer arranged under the flexible conductive layer and attached with a second adhesive to the flexible conductive layer, the intermediate insulating layer having second openings, a plurality of heat-conductive elements arranged inside the second openings, a first thin heat sink layer, the heat-conductive elements arranged to be in contact with an upper surface of the thin heat sink layer and the lower surface of the islands via heat-conductive material; and a second thin heat sink layer, upper surfaces of the power electronic devices arranged to be in contact with a lower surface of the thin heat sink layer and the lower surface of the islands via heat-conductive material.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicants: POWER GOLD LLC, SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: James Jen-Ho WANG, Jin Joo PARK
  • Publication number: 20140167618
    Abstract: Intelligent lighting system 100 is configured to operate from an AC source 12. An array of visible light emitting diodes (LEDs) 124 responds to environmental room conditions monitored by a sensor circuit. A microcontroller 146 operates in response to sensor circuit communications to control the state of the visible light array. An internal low noise voltage source VL is derived from the waste heat product from a portion of the LED array. The low noise voltage source is used to power the sensor circuit and the microcontroller.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Inventor: James Jen-Ho Wang
  • Publication number: 20120320532
    Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.
    Type: Application
    Filed: March 27, 2012
    Publication date: December 20, 2012
    Inventor: James Jen-Ho Wang
  • Patent number: 8153510
    Abstract: In a semiconductor wafer, the polyimide film underneath a power metal structure is partially etched to create corresponding surface depressions of the conformal top power metal. The depressions at the surface of power metal are visible under optical microscopy. Arrangement of the depressions in a pattern facilitates the alignment of probe needles, set-up of automated wire bonding and microscopic inspection for precise alignment of wire bonds.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: April 10, 2012
    Assignee: Power Gold LLC
    Inventor: James Jen-Ho Wang
  • Publication number: 20120061796
    Abstract: A mechanically programmable anti-fuse is configured in a thick, top metallic layer of a semiconductor. The metallic layer is selected of a material that possesses malleable properties. The metal anti-fuse programming pad is surrounded, either wholly or in part, by a pad segment. An intervening space between the anti-fuse pad and the pad segment is selected from a predetermined value such that capillary pressure, exerted when a ball-bond is placed atop the anti-fuse pad and the pad segment, causes the pads to deform and shorts to the anti-fuse pad to the pad segment. The shorting, created during the wire bonding process, programs the anti-fuse.
    Type: Application
    Filed: September 14, 2010
    Publication date: March 15, 2012
    Inventor: James Jen-Ho Wang
  • Patent number: 7868729
    Abstract: A stacked semiconductor device assembly (20) includes a device (24) having conductive traces (34) formed therein, and conductive interconnects (28) electrically connected to the conductive traces (34). Another device (26) has conductive traces (44) formed therein and device pads (54) formed on an outer surface (52) of the device (26). A method (120) entails attaching (84) a magnetic core (30) to an outer surface (42) of the device (24) and forming (92) the conductive interconnects (28) on the outer surface (42) using a stud bumping technique such that the interconnects (28) surround the magnetic core (30). The conductive interconnects (28) are coupled (126) with the device pads (54) using thermocompression bonding to couple the device (26) with the device (24) to form a continuous device coil (22) wrapped around the magnetic core (30) from an alternating electrical connection of the traces (34), the conductive interconnects (28), and the traces (44).
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: January 11, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James Jen-Ho Wang, Carl E. D'Acosta, Justin E. Poarch
  • Publication number: 20100301452
    Abstract: A high value capacitance per unit area capacitor is fabricated on a substrate 1 by converting a portion of a primary function anti-reflecting conducting layer 36 to a high value dielectric layer 37 by partially oxidizing the conducting layer to form the dielectric layer. The resultant combination is sandwiched between two metal layer electrodes 35 and 55 to complete the capacitor structure.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 2, 2010
    Inventor: James Jen-Ho Wang
  • Patent number: D732731
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: June 23, 2015
    Inventor: James Jen-Ho Wang