Abstract: An on-chip multiple-stage electrical overstress (EOS) protection device is disclosed. The protection device includes a surge protector having a first clamping voltage and a first electrostatic discharge (ESD) protector having a second clamping voltage lower than the first clamping voltage. The surge protector is electrically connected to the first ESD protector in parallel. The surge protector and the first ESD protector are electrically connected between a receiving terminal and a voltage terminal, and the receiving terminal is electrically connected to an internal circuit. When an electrical overstress (EOS) signal including an electrostatic discharge (ESD) signal and a surge signal appears at the receiving terminal, the first ESD protector and the surge protector are triggered on in turn to clamp a voltage received by the internal circuit.

Abstract: An on-chip multiple-stage electrical overstress (EOS) protection device is disclosed. The protection device includes a surge protector having a first clamping voltage and a first electrostatic discharge (ESD) protector having a second clamping voltage lower than the first clamping voltage. The surge protector is electrically connected to the first ESD protector in parallel. The surge protector and the first ESD protector are electrically connected between a receiving terminal and a voltage terminal, and the receiving terminal is electrically connected to an internal circuit. When an electrical overstress (EOS) signal including an electrostatic discharge (ESD) signal and a surge signal appears at the receiving terminal, the first ESD protector and the surge protector are triggered on in turn to clamp a voltage received by the internal circuit.

Abstract: A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval.

Abstract: A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval.

Abstract: A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval.

Abstract: A self-balanced silicon-controlled rectification device includes a substrate, an N-type doped well, a P-type doped well, at least one heavily doped clamping fin, at least one first P-type heavily doped fin, and at least one first N-type heavily doped fin. The N-type doped well and the P-type doped well are arranged in the substrate. The heavily doped clamping fin is arranged in the N-type doped well and the P-type well and protruded up from a surface of the substrate. The first P-type heavily doped fin and the first N-type heavily doped fin are respectively arranged in the N-type doped well and the P-type doped well, and protruded up from the surface of the substrate. The abovementioned elements forms silicon-controlled rectifiers (SCRs) are forward biased to generate uniform electrostatic discharge (ESD) currents through the SCRs.

Abstract: A bipolar transistor device includes a substrate and at least one first transistor unit. The first transistor unit includes a first doped well of first conductivity type, at least one first fin-based structure and at least one second fin-based structure. The first fin-based structure includes a first gate strip and first doped fins arranged in the first doped well, and the first gate strip is floating. The second fin-based structure includes a second gate strip and second doped fins arranged in the first doped well, and the second gate strip is floating. The first doped fins, the second doped fins and the first doped well form first BJTs, and the first doped fins and the second doped fins are respectively coupled to high and low voltage terminals.

Abstract: A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

Abstract: A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

Abstract: A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

Abstract: A low-cost ESD protection device for high-voltage open-drain pad is disclosed, which has a first high-voltage (HV) NMOSFET coupled to a high-voltage (HV) open drain pad, a ground pad, a HV block unit and an ESD clamp unit and a low-voltage (LV) bias unit coupled to the first HV NMOSFET, a low-voltage (LV) trigger, the ESD clamp unit and the ground pad. The LV trigger is coupled to the HV block unit. The HV block unit blocks a high voltage from the HV open drain pad diode during normal operation and generates a trigger signal to the LV trigger when an ESD event is applied to the HV open drain pad. Then, the LV trigger turns on the ESD clamp unit to discharge an ESD current and switches the LV bias unit to turn off the first HV NMOSFET.

Abstract: A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

Abstract: A high voltage open-drain electrostatic discharge (ESD) protection device is disclosed, which comprises a high-voltage n-channel metal oxide semiconductor field effect transistor (HV NMOSFET) coupled to a high-voltage pad and a low-voltage terminal and receiving a high voltage on the high-voltage pad to operate in normal operation. The high-voltage pad and the HV NMOSFET are further coupled to a high-voltage ESD unit blocking the high voltage, and receiving a positive ESD voltage on the high-voltage pad to bypass an ESD current when an ESD event is applied to the high-voltage pad. The high-voltage ESD unit and the low-voltage terminal are coupled to a power clamp unit, which receives the positive ESD voltage via the high-voltage ESD unit to bypass the ESD current.

Abstract: A high voltage open-drain electrostatic discharge (ESD) protection device is disclosed, which comprises a high-voltage n-channel metal oxide semiconductor field effect transistor (HV NMOSFET) coupled to a high-voltage pad and a low-voltage terminal and receiving a high voltage on the high-voltage pad to operate in normal operation. The high-voltage pad and the HV NMOSFET are further coupled to a high-voltage ESD unit blocking the high voltage, and receiving a positive ESD voltage on the high-voltage pad to bypass an ESD current when an ESD event is applied to the high-voltage pad. The high-voltage ESD unit and the low-voltage terminal are coupled to a power clamp unit, which receives the positive ESD voltage via the high-voltage ESD unit to bypass the ESD current.