Abstract: A sole structure for an article of footwear is provided. The sole structure includes a first midsole portion, a second midsole portion, and a sheet. The first midsole portion includes a first sidewall. The second midsole portion includes a second sidewall. The sheet is disposed between the first midsole portion and the second midsole portion and extends from the first sidewall and the second sidewall. The sheet extends at least partially over the second sidewall.

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

Abstract: Disclosed herein are line patterning techniques for integrated circuit (IC) devices, as well as related devices and assemblies In some embodiments, a patterned line region of an IC device may include: a first conductive line; a second conductive line parallel to the first conductive line; a conductive bridge between the first conductive line and the second conductive line, wherein the conductive bridge is coplanar with the first conductive line and the second conductive line; and pitch-division artifacts.

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

Abstract: In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness.

Abstract: In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness.

Abstract: A method for fabricating sub-resolution features on an integrated circuit comprises depositing a hard mask layer on a dielectric layer of a semiconductor substrate, patterning the hard mask layer to form hard mask structures that define trenches, etching trenches in the dielectric layer through the hard mask structures, thereby forming a first set of dielectric structures on the substrate, depositing a conformal layer on the substrate and the first set of dielectric structures, etching the conformal layer to form spacers adjacent to the first set of dielectric structures, depositing a second dielectric layer within the trenches, thereby forming a second set of dielectric structures on the substrate, and etching the spacers to form sub-resolution trenches between the dielectric structures of the first and second set.

Abstract: A method of forming a microelectronic structure and its associated structures is described. That method comprises forming and patterning a deep uv resist layer on a substrate, etching the substrate in a plasma generated from a gas comprising a carbon to fluorine ratio from about 1:1 to about 2:3 to form substantially vertical sidewalls in the deep uv resist layer.

Abstract: A method of forming a microelectronic structure and its associated structures is described. That method comprises forming and patterning a deep uv resist layer on a substrate, etching the substrate in a plasma generated from a gas comprising a carbon to fluorine ratio from about 1:1 to about 2:3 to form substantially vertical sidewalls in the deep uv resist layer.

Abstract: In one embodiment a method is provided. The method, comprises performing at least one deposition operation to laminate portions of a patterned photoresist that experiences degradation when bombarded with an etchant plasma during a subsequent plasma etching operation and performing the plasma etching operation.

Abstract: A method of forming a microelectronic structure and its associated structures is described. That method comprises forming and patterning a deep uv resist layer on a substrate, etching the substrate in a plasma generated from a gas comprising a carbon to fluorine ratio from about 1:1 to about 2:3 to form substantially vertical sidewalls in the deep uv resist layer.