Patents by Inventor James Juen Hsu
James Juen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9812503Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.Type: GrantFiled: August 15, 2016Date of Patent: November 7, 2017Assignee: HGST, Inc.Inventors: Daniel R. Shepard, Mac D. Apodaca, Thomas Michael Trent, James Juen Hsu
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Publication number: 20160351627Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.Type: ApplicationFiled: August 15, 2016Publication date: December 1, 2016Inventors: Daniel R. SHEPARD, Mac D. APODACA, Thomas Michael TRENT, James Juen HSU
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Patent number: 9431460Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.Type: GrantFiled: June 8, 2015Date of Patent: August 30, 2016Assignee: HGST, Inc.Inventors: Daniel R. Shepard, Mac D. Apodaca, Thomas Michael Trent, James Juen Hsu
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Publication number: 20160020253Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.Type: ApplicationFiled: June 8, 2015Publication date: January 21, 2016Inventors: Daniel R. SHEPARD, Mac D. APODACA, Thomas Michael TRENT, James Juen HSU
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Patent number: 9054031Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.Type: GrantFiled: June 17, 2014Date of Patent: June 9, 2015Assignee: CONTOUR SEMICONDUCTOR, INC.Inventors: Daniel R. Shepard, Mac D. Apodaca, Thomas Michael Trent, James Juen Hsu
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Publication number: 20140335669Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.Type: ApplicationFiled: June 17, 2014Publication date: November 13, 2014Inventors: Daniel R. Shepard, Mac D. Apodaca, Thomas Michael Trent, James Juen Hsu
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Patent number: 8786023Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.Type: GrantFiled: December 7, 2012Date of Patent: July 22, 2014Assignee: Contour Semiconductor, Inc.Inventors: Daniel R. Shepard, Mac D. Apodaca, Thomas Michael Trent, James Juen Hsu
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Publication number: 20140158963Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.Type: ApplicationFiled: December 7, 2012Publication date: June 12, 2014Applicant: Contour Semiconductor, Inc.Inventors: Daniel R. Shepard, Mac D. Apodaca, Thomas Michael Trent, James Juen Hsu
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Patent number: 6969686Abstract: A method for manufacturing a memory device utilizes multi-etching processes to respectively construct isolation trenches in a memory substrate that has a memory array area and a peripheral circuit region, wherein the depth of the trenches in the peripheral circuit region is deeper into the memory substrate than the depth of the trenches in the memory array area. Therefore, possible current leakage caused from the high operating voltage is effectively mitigated, and the performance of the memory device is increased.Type: GrantFiled: January 28, 2003Date of Patent: November 29, 2005Assignee: Winbond Electronics Corp.Inventors: Wen-Kuei Hsieh, Chih-Mu Huang, James Juen Hsu
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Patent number: 6862219Abstract: A weak programming method of a non-volatile memory. A first voltage is applied to a substrate during a first duration, while a control-gate voltage, such as zero volt, is applied to the gate, such that the leakage of the bit line is reduced and electron-hole pairs are generated. In the second duration, a second voltage is applied to the substrate, and a third voltage is applied to the gate to enhance the capability of injecting electrons into the floating gate of the non-volatile memory. Therefore, the distribution of the threshold voltage is more concentrated. The second voltage has a polarity the same as that of the first voltage, while the polarity of the third voltage is opposite to that of the second voltage.Type: GrantFiled: March 19, 2003Date of Patent: March 1, 2005Assignee: Winbond Electronics Corp.Inventors: Shih-Hsien Yang, Chien-Min Wu, James Juen Hsu, Chi-Moon Huang
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Patent number: 6858501Abstract: An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.Type: GrantFiled: April 14, 2003Date of Patent: February 22, 2005Assignee: Winbond Electronics CorporationInventor: James Juen Hsu
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Publication number: 20040092115Abstract: A method for manufacturing a memory device utilizes multi-etching processes to respectively construct isolation trenches in a memory substrate that has a memory array area and a peripheral circuit region, wherein the depth of the trenches in the peripheral circuit region is deeper into the memory substrate than the depth of the trenches in the memory array area. Therefore, possible current leakage caused from the high operating voltage is effectively mitigated, and the performance of the memory device is increased.Type: ApplicationFiled: January 28, 2003Publication date: May 13, 2004Applicant: Winbond Electronics Corp.Inventors: Wen-Kuei Hsieh, Chih-Mu Huang, James Juen Hsu
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Patent number: 6700165Abstract: A semiconductor structure with common source line, the semiconductor structure has two word lines, some bit lines, a silicon-based layer and a suicide layer. The silicon-based layer is located between and electrically separated from these word lines, but is electrically coupled with these bit lines. The silicide layer is located over and electrically coupled with the silicon-based layer. Moreover, suicide layer and silicide layer could be replaced by a silicon-base conductor layer, and are directly electrically coupled with some separated doped regions that located inside a substrate.Type: GrantFiled: October 25, 2002Date of Patent: March 2, 2004Assignee: Winbond Electronics CorporationInventors: Po-An Chen, James Juen Hsu
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Publication number: 20030168692Abstract: An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.Type: ApplicationFiled: April 14, 2003Publication date: September 11, 2003Applicant: Winbond Electronics CorporationInventor: James Juen Hsu
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Publication number: 20030107078Abstract: An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.Type: ApplicationFiled: February 8, 2002Publication date: June 12, 2003Applicant: Winbond Electronics CorporationInventor: James Juen Hsu
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Publication number: 20010014507Abstract: The present invention provides a method of forming a dual local oxidation structure (LOCOS) of a memory circuit in a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and non-overlapping first and second areas defined on the surface of the silicon substrate. The first area is used for forming a memory array of the memory circuit and the second area is used for forming a peripheral circuit of the memory circuit for controlling the operation of the memory array. Using this method, a pad oxide layer and a silicon nitride layer are first formed on the silicon substrate. The silicon nitride layer has a plurality of recesses extending down to the surface of the silicon substrate. The widths of the recesses in the first area are narrower than the widths of the recesses in the second area. Then, a high temperature oxidation process is performed to form a field oxide layer on the surface of the silicon substrate within each of the recesses.Type: ApplicationFiled: July 2, 1999Publication date: August 16, 2001Inventor: JAMES JUEN HSU
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Patent number: 5680345Abstract: A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.Type: GrantFiled: June 6, 1995Date of Patent: October 21, 1997Assignee: Advanced Micro Devices, Inc.Inventors: James Juen Hsu, Steven W. Longcor, Jih-Chang Lien
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Patent number: 5661055Abstract: A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.Type: GrantFiled: June 7, 1995Date of Patent: August 26, 1997Assignee: Advanced Micro Devices, Inc.Inventors: James Juen Hsu, Steven W. Longcor, Jih-Chang Lien
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Patent number: 5656513Abstract: A memory device, such as a flash EEPROM, employs a high energy implantation to form common source line, avoiding the necessity of self-aligned source etch processes. The use of the high energy implantation, and avoiding the etching process, provides for greater cell uniformity, and better V.sub.T distribution.Type: GrantFiled: June 7, 1995Date of Patent: August 12, 1997Assignee: Advanced Micro Devices, Inc.Inventors: Hsingya Arthur Wang, James Juen Hsu