Abstract: Apparatuses for a flip-flop are provided. One apparatus for a flip-flop includes a domino logic flip-flop, including a single footer transistor for all nodes in the domino logic flip-flop to be pre-charged, wherein the single footer includes a footer node; and a pre-charge transistor connected to the footer node for pre-charging the footer node before an evaluation cycle. Another apparatus for a flip-flop includes a domino logic flip-flop; and combinatory logic configured to evaluate a complimentary signal in conjunction with circuit events.

Abstract: Embodiments include an integrated clock gating (ICG) cell. The low power ICG cell may include an input condition determination circuit configured to generate a temporary inverted clock signal and an inverted output signal. The low power ICG cell may include an enable control logic circuit configured to receive the temporary inverted clock signal and the inverted output signal from the input condition determination circuit. The low power ICG cell may include a latch circuit coupled to the enable control logic circuit and configured to latch an input value dependent on at least the inverted output signal and the temporary inverted clock signal. The input condition determination circuit is configured to generate the temporary inverted clock signal only when it is needed.

Abstract: Embodiments include an integrated clock gating (ICG) cell. The low power ICG cell may include an input condition determination circuit configured to generate a temporary inverted clock signal and an inverted output signal. The low power ICG cell may include an enable control logic circuit configured to receive the temporary inverted clock signal and the inverted output signal from the input condition determination circuit. The low power ICG cell may include a latch circuit coupled to the enable control logic circuit and configured to latch an input value dependent on at least the inverted output signal and the temporary inverted clock signal. The input condition determination circuit is configured to generate the temporary inverted clock signal only when it is needed.

Abstract: According to one general aspect, an apparatus may include a latch, and a control circuit. The latch may receive an input enable signal and generate a latched enable signal. The latch may also pass the input enable signal to the latched enable signal when the latch is transparent. The control circuit may be electrically coupled to the latch. The control circuit may receive as input an ungated clock signal, and generate a gated clock signal and a latch control signal. The latch control signal may be configured to make the latch transparent when the ungated clock signal is in a predefined state and when one of the input enable signal and the latched enable signal are in an enabled state. The control circuit may be configured to pass the ungated clock signal to the gated clock signal when the latched enable signal is in the enabled state.

Abstract: According to one general aspect, an apparatus may include a latch, and a control circuit. The latch may receive an input enable signal and generate a latched enable signal. The latch may also pass the input enable signal to the latched enable signal when the latch is transparent. The control circuit may be electrically coupled to the latch. The control circuit may receive as input an ungated clock signal, and generate a gated clock signal and a latch control signal. The latch control signal may be configured to make the latch transparent when the ungated clock signal is in a predefined state and when one of the input enable signal and the latched enable signal are in an enabled state. The control circuit may be configured to pass the ungated clock signal to the gated clock signal when the latched enable signal is in the enabled state.

Abstract: Apparatuses for a flip-flop are provided. One apparatus for a flip-flop includes a domino logic flip-flop, including a single footer transistor for all nodes in the domino logic flip-flop to be pre-charged, wherein the single footer includes a footer node; and a pre-charge transistor connected to the footer node for pre-charging the footer node before an evaluation cycle. Another apparatus for a flip-flop includes a domino logic flip-flop; and combinatory logic configured to evaluate a complimentary signal in conjunction with circuit events.

Abstract: An apparatus for an integrated clock gating cell is provided. The apparatus includes a logic gate that receives an unbuffered enable signal (E), a scan test enable signal (SE), and outputs an inverted enable signal (EN); a first transmission gate that receives E, SE, and EN; a second transmission gate that is connected to the first transmission gate and receives a clock signal (CK) and an enabled and inverted clock signal (ECKN); a first transistor having terminals connected to a power supply voltage (VDD), an output of the logic gate, and the first transmission gate respectively; a second transistor including terminals connected to the first transmission gate and VDD respectively; and a latch including terminals connected to the second transmission gate and the second transistor respectively.