Abstract: A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF.

Abstract: A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF.

Abstract: A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be on to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn on. After the at least one IGBT turns on, the at least one GTO is configured to turn off. After a predetermined amount of time after the at least one GTO turns off, the at least one IGBT is configured to turn off.

Abstract: A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF.

Abstract: A circuit for transferring parasitic energy to an external load. The circuit includes a first array of semiconductor switches connected in parallel with one another, a second array of semiconductor switches connected in parallel with one another, an external load connected in parallel with the second array of semiconductor switches, an extended-time saturable reactor (ETSR), and a voltage snubber capacitor. The second array of semiconductor switches is connected in series with the first array of semiconductor switches. The ETSR is connected in series with the second array of semiconductor switches. The voltage snubber capacitor is connected in parallel with the second array of semiconductor switches and the ETSR. The circuit may further include an energy return circuit including an isolation transformer for returning energy in the voltage snubber capacitor to the external load. The external load can include a capacitive load or an external power supply.

Abstract: A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF.

Abstract: A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be on to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn on. After the at least one IGBT turns on, the at least one GTO is configured to turn off. After a predetermined amount of time after the at least one GTO turns off, the at least one IGBT is configured to turn off.

Abstract: A power pack for providing power electronics at high temperature with high dI/dt, current, and voltage capability. The power pack having three layers. A top layer for providing: a matching composite Coefficient of Thermal Expansion (CTE) between power device materials and power electrodes, thermal cooling, and electrical conduction paths. The top layer may have interface circuitry for driving and controlling on-board power semiconductor devices. The top layer may also include traces and pads for the attachment of a gate, a gate return, and terminals. A middle layer may be a power semiconductor device providing control of the current flow. The bottom layer may be a rigid base plate for providing structural rigidity or may provide an electric and thermal path for the power semiconductor device. The power pack also includes a thermal shim which provides a thermal path to dissipate heat generated by the interface circuitry. The power pack may also include a snubber circuit.

Abstract: A circuit and method for interrupting an AC load current includes a first MOS Controlled Thyristor (MCT) for selectively interrupting the load current. The current through the first MCT is reduced when the load current is to be interrupted by providing a pulse resonant commutation (PRC) current through the first MCT which flows in a direction opposed to the AC load current direction and which has a magnitude reducing the current through the first MCT to an MCT "off" condition (e.g., when a voltage across the MCT is reversed, when there is near zero current through the MCT, or when a current is within the MCT's SOA.) The first MCT turns itself off when MCT gate voltage is an "on" voltage and when reverse voltage is across the MCT. An MCT "off" voltage may then be provided by sensing MCT current and providing an "off" voltage to the MCT gate when the sensed current indicates that the MCT is an "off" condition.