Patents by Inventor James K. Brence

James K. Brence has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test unit and enclosure for testing integrated circuits
    Patent number: 6781053
    Abstract: In a die test unit the accumulation of static charge on an enclosure is substantially avoided by fabricating the enclosure to have smooth surfaces coated with a conductive material, insulating the coated or conductive surfaces of the enclosure from the test fixture, and coupling the coated or conductive surfaces to the ground. Any charge that accumulates on the coated or conductive surface of the enclosure is discharged along a conductive path to a reference potential typically formed by a connector, a ground conductor, and a ground. The enclosure supports a substantially laminar air flow over a die by providing a smooth inner surface and two or more vent holes formed about half way between a first end and a second end of the enclosure. The substantially laminar air flow assists in maintaining the air surrounding the die at a substantially constant temperature.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: August 24, 2004
    Assignee: Intel Corporation
    Inventors: Richard W. Ollila, James K. Brence
  • Test unit and enclosure for testing integrated circuits
    Publication number: 20040046584
    Abstract: In a die test unit the accumulation of static charge on an enclosure is substantially avoided by fabricating the enclosure to have smooth surfaces coated with a conductive material, insulating the coated or conductive surfaces of the enclosure from the test fixture, and coupling the coated or conductive surfaces to the ground. Any charge that accumulates on the coated or conductive surface of the enclosure is discharged along a conductive path to a reference potential typically formed by a connector, a ground conductor, and a ground. The enclosure supports a substantially laminar air flow over a die by providing a smooth inner surface and two or more vent holes formed about half way between a first end and a second end of the enclosure. The substantially laminar air flow assists in maintaining the air surrounding the die at a substantially constant temperature.
    Type: Application
    Filed: September 8, 2003
    Publication date: March 11, 2004
    Applicant: Intel Corporation
    Inventors: Richard W. Ollila, James K. Brence
  • Test unit and enclosure for testing integrated circuits
    Patent number: 6628131
    Abstract: In a die test unit the accumulation of static charge on an enclosure is substantially avoided by fabricating the enclosure to have smooth surfaces coated with a conductive material, insulating the coated or conductive surfaces of the enclosure from the test fixture, and coupling the coated or conductive surfaces to the ground. Any charge that accumulates on the coated or conductive surface of the enclosure is discharged along a conductive path to a reference potential typically formed by a connector, a ground conductor, and a ground. The enclosure supports a substantially laminar air flow over a die by providing a smooth inner surface and two or more vent holes formed about half way between a first end and a second end of the enclosure. The substantially laminar air flow assists in maintaining the air surrounding the die at a substantially constant temperature.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: September 30, 2003
    Assignee: Intel Corporation
    Inventors: Richard W. Ollila, James K. Brence