Patents by Inventor James K. Falbo

James K. Falbo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11734487
    Abstract: A computing system may include a metal stack tuning engine and a tuned metal stack application engine. The metal stack tuning engine may be configured to access an obscured metal stack definition specified for an integrated circuit (IC) manufacture process and tune selected metal stack parameters of the obscured metal stack definition to obtain a tuned metal stack definition. The metal stack tuning engine may do so by generating sampled metal stack definitions, constructing sampled layout geometries from the sampled metal stack definitions, computing parasitic capacitance value sets for the sampled layout geometries, and determining tuned values for the selected metal stack parameters through a curve fitting process. The tuned metal stack application engine may be configured to use the tuned metal stack definition to perform a parasitic capacitance extraction process for an input IC design.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: August 22, 2023
    Assignee: Siemens Industry Software Inc.
    Inventors: Mohamed Saleh Abouelyazid Saleh, James K. Falbo
  • Publication number: 20220382952
    Abstract: A computing system may include a metal stack tuning engine and a tuned metal stack application engine. The metal stack tuning engine may be configured to access an obscured metal stack definition specified for an integrated circuit (IC) manufacture process and tune selected metal stack parameters of the obscured metal stack definition to obtain a tuned metal stack definition. The metal stack tuning engine may do so by generating sampled metal stack definitions, constructing sampled layout geometries from the sampled metal stack definitions, computing parasitic capacitance value sets for the sampled layout geometries, and determining tuned values for the selected metal stack parameters through a curve fitting process. The tuned metal stack application engine may be configured to use the tuned metal stack definition to perform a parasitic capacitance extraction process for an input IC design.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 1, 2022
    Inventors: Mohamed Saleh Abouelyazid Saleh, James K. Falbo
  • Patent number: 8250517
    Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: August 21, 2012
    Assignee: Synopsys, Inc.
    Inventors: James K. Falbo, Vinod K. Malhotra, Pratheep Balasingam, Donald Zulch
  • Publication number: 20100115481
    Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.
    Type: Application
    Filed: January 13, 2010
    Publication date: May 6, 2010
    Applicant: Synopsys, Inc.
    Inventors: James K. Falbo, Vinod K. Malhotra, Pratheep Balasingam, Donald Zulch
  • Patent number: 7669169
    Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: February 23, 2010
    Assignee: Synopsys, Inc.
    Inventors: James K. Falbo, Vinod K. Malhotra, Pratheep Balasingam, Donald Zulch
  • Patent number: 7159197
    Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: January 2, 2007
    Assignee: Synopsys, Inc.
    Inventors: James K. Falbo, Vinod K. Malhotra, Pratheep Balasingam, Donald Zulch
  • Publication number: 20030163791
    Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.
    Type: Application
    Filed: December 31, 2001
    Publication date: August 28, 2003
    Applicant: Numerical Technologies, Inc.
    Inventors: James K. Falbo, Vinod K. Malhotra, Pratheep Balasingam, Donald Zulch