Abstract: A method of forming a plurality of conductive studs within a non-planar insulator layer (e.g., PSG or BPSG) disposed between a first series of conductive structures arranged on a substrate and metal lines formed on the upper surface of the insulator layer. Vertical vias are defined through the insulator layer to expose at least one of the first conductive structures on the substrate. A conformal metal layer (e.g., CVD W) is deposited on the insulator layer to fill the vias. Then, the metal layer and the insulator layer subjected to a polish etch in the presence of an abrasive slurry, to remove portions of the metal layer outside of the vias while simultaneously planarizing the insulator layer.

Abstract: A polishing tool for abrasively polishing a semiconductor wafer that edge clamps the wafer between two rollers. The wafer is spun-up in one plane and the rollers spin in a second plane which is orthogonal to the wafer spin plane. One of the rollers is split with each section rotating in opposite directions. Each of the rollers is mounted by a spring-gimballed assembly to follow the wafer contour.