Patents by Inventor James K. Schaeffer
James K. Schaeffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8853792Abstract: Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.Type: GrantFiled: January 5, 2012Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Murshed M. Chowdhury, James K. Schaeffer
-
Patent number: 8735996Abstract: A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.Type: GrantFiled: July 12, 2012Date of Patent: May 27, 2014Assignees: International Business Machines Corporation, Globalfoundries Inc.Inventors: Takashi Ando, Unoh Kwon, Vijay Narayanan, James K. Schaeffer
-
Patent number: 8716088Abstract: A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.Type: GrantFiled: June 27, 2012Date of Patent: May 6, 2014Assignees: International Business Machines Corporation, GLOBAL FOUNDRIES Inc.Inventors: Takashi Ando, Unoh Kwon, Vijay Narayanan, James K. Schaeffer
-
Publication number: 20140001573Abstract: A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.Type: ApplicationFiled: July 12, 2012Publication date: January 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Unoh Kwon, Vijay Narayanan, James K. Schaeffer
-
Publication number: 20140004695Abstract: A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Unoh Kwon, Vijay Narayanan, James K. Schaeffer
-
Patent number: 8415212Abstract: A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.Type: GrantFiled: March 11, 2010Date of Patent: April 9, 2013Assignee: Freescale Semiconductor, Inc.Inventors: James K. Schaeffer, Eric D. Luckowski, Todd C. Bailey, Amy L. Child, Daniel Jaeger, Renee Mo, Ying H. Tsang
-
Patent number: 8309419Abstract: A method and apparatus are described for fabricating single metal gate electrodes (35, 36) over a high-k gate dielectric layer (31, 32) that is separately doped in the PMOS and NMOS device areas (96, 97) by forming first capping oxide layer (23) with a first dopant species on a high-k gate dielectric layer (22) in at least the NMOS device area and also forming second capping oxide layer (27) with a second dopant species on a high-k gate dielectric layer (22) in at least the PMOS device area, where the first and second dopant species are diffused into the gate dielectric layer (22) to form a first fixed charge layer (31) in the PMOS device area of the high-k gate dielectric area and a second fixed charge layer (32) in the NMOS device area of the high-k gate dielectric area.Type: GrantFiled: February 4, 2009Date of Patent: November 13, 2012Assignee: Freescale Semiconductor, Inc.Inventors: James K. Schaeffer, Eric D. Luckowski
-
Publication number: 20120104515Abstract: Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.Type: ApplicationFiled: January 5, 2012Publication date: May 3, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Murshed M. Chowdhury, James K. Schaeffer
-
Patent number: 8114739Abstract: Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material overlying the oxygen-diffusion barrier layer, forming a layer of conductive material overlying the layer of high-k dielectric material, selectively removing portions of the layer of conductive material, the layer of high-k dielectric material, the oxygen-diffusion barrier layer, and the oxide layer to form a gate stack, and forming source and drain regions about the gate stack. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.Type: GrantFiled: September 28, 2009Date of Patent: February 14, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Murshed M. Chowdhury, James K. Schaeffer
-
Publication number: 20110223756Abstract: A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.Type: ApplicationFiled: March 11, 2010Publication date: September 15, 2011Inventors: James K. Schaeffer, Eric D. Luckowski, Todd C. Bailey, Amy L. Child, Daniel Jaeger, Renee Mo, Ying H. Tsang
-
Publication number: 20110073964Abstract: Methods and apparatus are provided for fabricating a transistor. The transistor comprises a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and an oxygen-gettering conductive layer overlying the high-k dielectric layer. The oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive layer.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Murshed M. Chowdhury, James K. Schaeffer
-
Patent number: 7910442Abstract: A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.Type: GrantFiled: July 24, 2007Date of Patent: March 22, 2011Assignee: Freescale Semiconductor, Inc.Inventors: William J. Taylor, Jr., Cristiano Capasso, Srikanth B. Samavedam, James K. Schaeffer
-
Publication number: 20100197128Abstract: A method and apparatus are described for fabricating single metal gate electrodes (35, 36) over a high-k gate dielectric layer (31, 32) that is separately doped in the PMOS and NMOS device areas (96, 97) by forming first capping oxide layer (23) with a first dopant species on a high-k gate dielectric layer (22) in at least the NMOS device area and also forming second capping oxide layer (27) with a second dopant species on a high-k gate dielectric layer (22) in at least the PMOS device area, where the first and second dopant species are diffused into the gate dielectric layer (22) to form a first fixed charge layer (31) in the PMOS device area of the high-k gate dielectric area and a second fixed charge layer (32) in the NMOS device area of the high-k gate dielectric area.Type: ApplicationFiled: February 4, 2009Publication date: August 5, 2010Inventors: James K. Schaeffer, Eric D. Luckowski
-
Patent number: 7683439Abstract: A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element.Type: GrantFiled: March 12, 2007Date of Patent: March 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Srikanth B. Samavedam, David C. Gilmer, Mark V. Raymond, James K. Schaeffer
-
Patent number: 7666730Abstract: A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.Type: GrantFiled: June 29, 2007Date of Patent: February 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Gauri V. Karve, Cristiano Capasso, Srikanth B. Samavedam, James K. Schaeffer, William J. Taylor, Jr.
-
Patent number: 7655550Abstract: A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.Type: GrantFiled: June 30, 2006Date of Patent: February 2, 2010Assignee: Freescale Semiconductor, Inc.Inventors: James K. Schaeffer, David C. Gilmer, Mark V. Raymond, Philip J. Tobin, Srikanth B. Samavedam
-
Patent number: 7648884Abstract: A resistive device (44) and a transistor (42) are formed. Each uses a portion of a metal layer (18) that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer (34) overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.Type: GrantFiled: February 28, 2007Date of Patent: January 19, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Byoung W. Min, James K. Schaeffer, David C. Sing
-
Publication number: 20090286387Abstract: A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (14) over a gate dielectric layer (12) and then selectively introducing nitrogen into the portions of the first conductive layer (14) in the PMOS device region (1), either by annealing (42) a nitrogen-containing diffusion layer (22) formed in the PMOS device region (1) or by performing an ammonia anneal process (82) while the NMOS device region (2) is masked. By introducing nitrogen into the first conductive layer (14), the work function is modulated toward PMOS band edge.Type: ApplicationFiled: May 16, 2008Publication date: November 19, 2009Inventors: David C. Gilmer, Srikanth B. Samavedam, James K. Schaeffer, Voon-Yew Thean
-
Publication number: 20090029538Abstract: A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.Type: ApplicationFiled: July 24, 2007Publication date: January 29, 2009Inventors: William J. Taylor, JR., Cristiano Capasso, Srikanth B. Samavedam, James K. Schaeffer
-
Publication number: 20090004792Abstract: A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: Gauri V. Karve, Cristiano Capasso, Srikanth B. Samavedam, James K. Schaeffer, William J. Taylor, JR.