Abstract: This disclosure is concerned with a process for connecting a short detector to electrical nodes in such apparatus as backplanes, cables, and circuit boards, before and after component assembly, to identify shorted node pairs in a substantially smaller number of tests than required by previously known methods, through a novel series of tests between each node and all other nodes, taken together, so as to identify shorted nodes, and then a series of tests between each of these shorted nodes and all other shorted nodes, taken individually, to identify the shorted node pairs.

Abstract: A method and apparatus are disclosed for identifying and locating faults in the portion of circuit assemblies containing digital signals by conducting in-circuit tests embodying the application of uninterrupted sequences of signals to nodes of the circuits and the comparison of nodal signals to expected values, reducing the complex testing of the circuit assemblies to a series of simple tests of components or groups of components constituting the assemblies; and, in connection with bus-structured circuits, eliminating the possibility of bus contention problems in good circuit assemblies under test.