Abstract: Technologies for a high gradient of dopant concentration in gate-all-around transistors are disclosed. In an illustrative embodiment, a source/drain region of a gate-all-around transistor may have a relatively high dopant concentration, such as a dopant concentration of over 1020 cm?3, and an adjacent channel region may have a relatively low dopant concentration, such as a dopant concentration of less than 1018 cm?3. At an interface between the source/drain region and the channel region, the logarithmic slope of the dopant concentration may be high, such as two orders of magnitude in less than a nanometer. In order to maintain such a high dopant concentration, the source/drain region with a high dopant concentration is deposited using a low-temperature deposition technique after high-temperature processing steps are completed.

Abstract: Integrated circuit structures having epitaxial nubs for uniform grid metal gate and trench contact cut are described. A structure includes a vertical stack of horizontal nanowires, individual ones of the nanowires having a corresponding epitaxial source or drain structure at an end of the nanowire, the epitaxial source or drain structures discontinuous with one another along the vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode, the conductive trench contact vertically surrounding individual ones of the epitaxial source or drain structures. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact.

Abstract: In some implementations, a device may include a channel material. In addition, the device may include a contact metal. The device may include a first layer between the channel material and the contact metal, the first layer having antimony and silicon. Moreover, the device may include a second layer between the contact metal and the first layer, the second layer having phosphorus and silicon.