Abstract: Described herein are truncated EGF receptor polypeptides, nucleic acids encoding them, and methods of using them to help select a method of treatment for an EGFR-related cancer, to predict clinical outcome, and to detect micrometastases or minimal residual disease. High EGFR expression and phosphorylated EGFR predicts poor survival in head and neck cancer patients, but does not correlate with advanced stage disease. In our studies, we determined that clinical biological correlates are likely to be more accurate when different aspects of EGFR are evaluated in combination. We analyzed EGFR phosphorylation, expression and mutations in 60 primary head and neck tumors. We not only found that head and neck tumors with either truncated or activated EGFR tend to have higher tumor and nodal stage, but also discovered three EGFR truncations.

Abstract: Described herein are truncated EGF receptor polypeptides, nucleic acids encoding them, and methods of using them to help select a method of treatment for an EGFR-related cancer, to predict clinical outcome, and to detect micrometastases or minimal residual disease. High EGFR expression and phosphorylated EGFR predicts poor survival in head and neck cancer patients, but does not correlate with advanced stage disease. In our studies, we determined that clinical biological correlates are likely to be more accurate when different aspects of EGFR are evaluated in combination. We analyzed EGFR phosphorylation, expression and mutations in 60 primary head and neck tumors. We not only found that head and neck tumors with either truncated or activated EGFR tend to have higher tumor and nodal stage, but also discovered three EGFR truncations.

Abstract: A facility for distributing electronic coupons is described. The facility presents to a user indications of each of at least one coupon pack. Each coupon pack comprises a plurality of independently-redeemable electronic coupons. The facility receives user input selecting an indicated coupon pack, and uses payment information associated with the user to collect a price indicated for the selected coupon pack. The facility then makes the selected coupon pack available for use by the user such that the user may redeem any of the electronic coupons of the selected coupon pack.

Abstract: A flooring system for radiant heating includes a top floor portion and a subfloor portion. The top portion is releasably connectable to the subfloor portion in a vertical direction substantially perpendicular to a walking surface of the top portion. The top portion includes a bottom side and top channel portion downwardly depending from the bottom side. The subfloor portion includes a top side and a bottom channel portion extending upwardly from the top side. The top channel portion and the bottom channel portion bound a channel for receiving a heating conduit. The channel extends longitudinally relative to the top floor portion and the subfloor portion.

Abstract: A wall covering system for radiant heating includes a first wall covering portion and a second wall covering portion. The first portion is releasably connectable to the second portion in a direction substantially perpendicular to an outer surface of the first portion. The first portion includes a bottom side and top channel portion downwardly depending from the bottom side. The second portion includes a top side and a bottom channel portion extending upwardly from the top side. The top channel portion and the bottom channel portion bound a channel for receiving a heating conduit. The channel extends longitudinally relative to the first portion and the second portion.

Abstract: A flooring system for radiant heating includes a top floor portion and a subfloor portion. The top portion is releasably connectable to the subfloor portion in a vertical direction substantially perpendicular to a walking surface of the top portion. The top portion includes a bottom side and top channel portion downwardly depending from the bottom side. The subfloor portion includes a top side and a bottom channel portion extending upwardly from the top side. The top channel portion and the bottom channel portion bound a channel for receiving a heating conduit. The channel extends longitudinally relative to the top floor portion and the subfloor portion.

Abstract: A multiple processor device stores a stream of data as a plurality of data segments, which includes multiplexed data fragments from at least one of a plurality of virtual channels. The data segments that comprise the stream of data correspond to the multiplexed data fragments from the virtual channels. The multiple processor device then decodes at least one data segment in accordance with one of a plurality of transmission protocols to produce a decoded data segment. The multiple processor device then stores the decoded data segment to align it in accordance with a data path segment size. The multiple processor device then interprets the stored decoded data segment with respect to a corresponding one of the plurality of virtual channels to determine a destination of the stored decoded data segment. The multiple processor device then stores the decoded data segment as part of reassembled data.

Abstract: In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments.

Abstract: A sheet feed roller system for reversing the sheet contact side of a sheet feed mechanism for an offset printing press. A traction roller is attached to a pivot shaft in the place of an idler roller. A non-traction roller is attached in the place of a drive roller. A transmission is provided having a rotary input connectable to the press for receiving rotational power from the press and having a rotary output. A variant axes drive mechanism with a first end and a second end is constructed so that the first end couples to the rotary output of the transmission. A power roller is attached and coupled to the second end of the variant axes drive mechanism and so that it pivots with the pivot shaft and remains in rotational contact with the traction roller to impart rotational power to the traction roller.

Abstract: A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.

Abstract: An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect.

Abstract: In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue.

Abstract: In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments.

Abstract: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

Abstract: In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.

Abstract: A waste water recovery system to filter and recirculate waste water to a wash system including a fluid recovery line, a fluid supply line and a fluid backwash line comprising a filter assembly including a water filtering section to receive waste water from the wash system and to recirculate filtered water to the wash system and a filter backwash section to selectively clean the water filtering section when a system condition exists, and a fluid control including a plurality of valve assemblies operatively coupled between the wash system, the water filtering section and the filter backwash section to selectively control the circulation of water through the water filtering section to recirculate the recovery water to the wash system and to periodically clean the water filtering section.

Abstract: A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (value) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.

Abstract: Identification devices and methods of producing the identification devices are presented. Some embodiments of identification devices comprise a structure having a micro-optic image and a layer that is overprinted onto the surface of the structure. In some embodiments, the structure is a substantially planar structure, such as a cardstock sheet, and the micro-optic image is a hologram. A web-fed flexographic printing process is presented, in which the process comprises the steps of providing a web, determining a feed rate for the web, feeding the web at the determined feed rate, and overprinting onto a surface of the web. In some embodiments, the web has a micro-optic structure and an eye-mark. The micro-optic structure is located at a predefined position on the web, and the eye-mark is located at a fixed position with reference to the position of the micro-optic structure. The feed rate is determined using the eye-mark. In some embodiments, the micro-optic structure is a hologram.

Abstract: An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the device to the central logic unit and the second unidirectional, point-to-point communication link transfers data from the central logic unit to the device.

Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.