Abstract: A method, apparatus, and system are disclosed for tuning core voltages of processors. One embodiment is a method for software execution. The method includes varying core voltages of plural processors operating in lockstep to determine an operating range for each of the plural processors, and adjusting the core voltages of the plural processors within the operating range to tune the plural processors.

Abstract: A method and system of executing duplicate copies of a program in lock step. Some illustrative embodiments are a computer system comprising a first processor executing a program, a second processor executing a duplicate copy of the program (the first processor and second processor executing their respective programs in lock step), a logic device coupled to the processors, and a shared device coupled to the processors through the logic device. The first processor presents to the logic device a first operation involving the shared device, and the second processor does not present an operation, or presents an operation that does not match the first operation. The logic device obtains a second operation from the second processor that matches the first operation, and wherein a single operation that matches the first and second operations is presented to the shared device.

Abstract: A method and system of presenting an interrupt request to processors executing in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor configured to execute a program, a second processor configured to execute a duplicate copy of the program in lock step with the first processor, and a logic device coupled to the processors. The logic device is configured to present an interrupt request to the processors when the processors are at substantially the same computational point in the program.

Abstract: A method and system of determining the execution point of programs executed in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor that executes a program, and a second processor that executes a duplicate copy of the program in lock step with the first processor. After receipt of a duplicate copy of an interrupt request by each processor, the first processor determines the execution point in its program relative to the execution point of the duplicate copy of the program executed by the second processor.

Abstract: A method and system of bringing processors to the same computational point. At least some of the illustrative embodiments are computer systems comprising a first processor executing a program, a second processor executing a duplicate copy of the program (but at different computational points in the program), and a shared main memory coupled to the first and second processors. When the processors each receive duplicate copies of an interrupt request, the processors are configured to bring their respective programs to the same computational points prior to servicing the interrupt request.

Abstract: A method and system of copying memory from a source processor to a target processor by duplicating memory writes. At least some of the exemplary embodiments may be a method comprising stopping execution of a user program on a target processor (the target processor coupled to a first memory), continuing to execute a duplicate copy of the user program on a source processor (the source processor coupled to a second memory and generating writes to the second memory), duplicating memory writes of the source processor and duplicating writes by input/output adapters to create a stream of duplicate memory writes, and applying the duplicated memory writes to the first memory.

Abstract: A method and system of copying a memory area between processor elements for lock-step execution. At least some of the illustrative embodiments may be a method comprising executing duplicate copies of a first program in a first processor of a first multiprocessor computer system and in a first processor of a second multiprocessor computer system (the executing substantially in lock-step), executing a second program in a second processor element of the first multiprocessor computer system (the first and second processors of the first multiprocessor computer system sharing an input/output (I/O) bridge), copying a memory area of the second program executing in the second processor element of the first multiprocessor computer system to a memory of a second processor element in the second multiprocessor computer system while the duplicate copies of the first program are executing in the first processor elements, and then executing duplicate copies of the second program in the second processors in lock-step.

Abstract: A method and system of servicing asynchronous interrupts in multiple processors executing a user program. Some of the exemplary embodiments may be a method comprising executing a user program on a first processor and a duplicate copy of the user program on a second processor, receiving an asynchronous interrupt by both the first and second processors, executing an interrupt service routine on the first processor at an agreed system call of the user program executed on the first processor, and executing an interrupt service routine on the second processor at the agreed system call of the user program executed on the second processor.

Abstract: A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.

Abstract: In a redundant-processor computing device, an error handling method comprises detecting equivalent disparity among processor elements of the computing device operating and responding to the detected equivalent disparity by evaluating secondary considerations of processor fidelity.

Abstract: A plurality of redundant, loosely-coupled processor elements are operational as a logical processor. A logic detects a halt condition of the logical processor and, in response to the halt condition, reintegrates and commences operation in less than all of the processor elements leaving at least one processor element nonoperational. The logic also buffers data from the nonoperational processor element in the reloaded operational processor elements and writes the buffered data to storage for analysis.

Abstract: A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.