Patents by Inventor James Koford

James Koford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050034086
    Abstract: The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a method for mapping platform-based design to multiple foundry processes may include the following steps. First, a virtual process is defined to include at least one fabrication process. A virtual process is a totality of variables associated with the population of candidate processes and any other process of interest, which might be purely hypothetical, that would be capable, in principle, of accommodating some or all slices. A virtual process may or may not be realized and is an abstract logical container for a population of processes. Then, the virtual process may be stored into a database. The virtual process may be in a representation including a list of attributes of entities making up the fabrication process. Next, optimization of the database may be performed using mathematical and statistical tools.
    Type: Application
    Filed: January 29, 2004
    Publication date: February 10, 2005
    Inventors: Christopher Hamlin, James Koford
  • Publication number: 20050034087
    Abstract: The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a method for mapping platform-based design to multiple foundry processes may include the following steps. First, availability of required features of a design in a target foundry process may be checked. The target foundry process must provide all the features that are used in the design. The design may include base wafer layers and metal stack layers. Then, a base wafer/metal stack interface layer for the design may be selected. Next, compatible blocks between different base wafer processes may be created. Then, a physical design library for the design may be created. Next, a logic design and timing library for the design may be created. This way, the design may be mapped to different foundry processes.
    Type: Application
    Filed: January 29, 2004
    Publication date: February 10, 2005
    Inventors: Christopher Hamlin, James Koford, Douglas Boyle
  • Patent number: 5838163
    Abstract: Signals (including probes) from an external system are selectively connected to a plurality of unsingulated dies on a semiconductor wafer with a minimum number of connections and an electronic selection mechanism resident on the wafer. The electronic selection mechanism is connected to the individual dies by conductive lines on the wafer. The electronic selection mechanism is capable of providing the external signals (or connecting the external probe) to a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively provide signals to the unsingulated dies.
    Type: Grant
    Filed: December 26, 1995
    Date of Patent: November 17, 1998
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Carlos Dangelo, James Koford
  • Patent number: 5648661
    Abstract: Unsingulated dies on a wafer may be individually electronically selected using various "electronic mechanisms" on the wafer. Conductive lines extend on the wafer from the electronic mechanism to the individual dies. The conductive lines may be provided in sets of two or more, such as for providing discrete power and ground connections from the external equipment to the individual dies. Redundant conductive lines may be provided to ensure against "open" faults. Diode and/or fuses may also be provided in conjunction with the conductive lines to ensure against leakages and shorts. Redundant electronic selection mechanisms may also be provided.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: July 15, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Carlos Dangelo, James Koford, Edwin Fulcher
  • Patent number: 5539325
    Abstract: Signals (including probes) from an external system are selectively connected to a plurality of unsingulated dies on a semiconductor wafer with a minimum number of connections and an electronic selection mechanism resident on the wafer. The electronic selection mechanism is connected to the individual dies by conductive lines on the wafer. The electronic selection mechanism is capable of providing the external signals (or connecting the external probe) to a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively provide signals to the unsingulated dies.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: July 23, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Carlos Dangelo, James Koford
  • Patent number: 5442282
    Abstract: Signals (including probes) from an external system are selectively connected to a plurality of unsingulated dies on a semiconductor wafer with a minimum number of connections and an electronic selection mechanism resident on the wafer. The electronic selection mechanism is connected to the individual dies by conductive lines on the wafer. The electronic selection mechanism is capable of providing the external signals (or connecting the external probe) to a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively provide signals to the unsingulated dies.
    Type: Grant
    Filed: July 2, 1992
    Date of Patent: August 15, 1995
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Carlos Dangelo, James Koford
  • Patent number: 5389556
    Abstract: A plurality of unsingulated dies on a wafer may be individually powered up using various "electronic mechanisms" on the wafer, and connecting the electronic mechanisms to the individual dies by conductive lines on the wafer. The electronic mechanisms are capable of powering-up a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively power up the dies.
    Type: Grant
    Filed: July 2, 1992
    Date of Patent: February 14, 1995
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Carlos Dangelo, James Koford