Abstract: Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.

Abstract: Methods and apparatus are provided for implementing circuitry operable to perform barrel shifting, multiplication, and rotation operations in hard coded logic on a programmable chip. A hard coded multiplier is augmented using multiplexer circuitry, a logical operation, and a bypassable 2^N functional block. Based on control signals, the multiplexer circuitry can be used to select a rotation, multiplication, or barrel shifted output. Multiplexer control signals also provide sign information associated with operands passed to the multiplier. A single augmented multiplier can perform barrel shifting, rotation, or multiplication operations. Inputs of a multiplier can also be selectively grounded to allow the multiplier to perform logic operations.

Abstract: Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.

Abstract: Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.

Abstract: Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.

Abstract: Methods and apparatus are provided for allowing a component such as a processor on a programmable chip efficient access to properly transformed data an embedded memory. Circuitry is provided with the read data port associated with an embedded memory. The circuitry can be used to perform both static bit width configuration of an embedded memory as well as perform data transformation or data alignment of embedded memory read data. The circuitry can allow efficient data transformations including selection of half words and bytes as well as perform sign extension and zero extension of memory read data.

Abstract: A system and a method for reducing interrupt latency is described. The system includes a first interrupt source configured to generate a first interrupt, a second interrupt source configured to generate a second interrupt, and a processor. The processor includes a shadow set that stores data used to service the first interrupt. The processor receives the second interrupt and receives a designation of the shadow set to service the second interrupt. The processor determines, based on a dedicated bit, whether the shadow set is used to service the first interrupt upon receiving the second interrupt.

Abstract: Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.

Abstract: Methods and apparatus are provided for implementing circuitry operable to perform barrel shifting, multiplication, and rotation operations in hard coded logic on a programmable chip. A hard coded multiplier is augmented using multiplexer circuitry, a logical operation, and a bypassable 2^N functional block. Based on control signals, the multiplexer circuitry can be used to select a rotation, multiplication, or barrel shifted output. Multiplexer control signals also provide sign information associated with operands passed to the multiplier. A single augmented multiplier can perform barrel shifting, rotation, or multiplication operations. Inputs of a multiplier can also be selectively grounded to allow the multiplier to perform logic operations.

Abstract: A distributed digital imaging processing system having a number of processing units and circular FIFO buffers connected together using data transforming streams. Processing units read data from buffers using a transforming read streams. These read streams reorder the buffer data to form patches representing neighborhood pixels and may provide the same data multiple times. After processing a patch, a processing unit writes the resultant patch into a buffer using a transforming write stream which reorders the data into the storage format of the buffer. Several buffers can feed a single processor and one processor can feed several buffers. All the details of each data stream (buffer, current buffer location, patch size, access pattern) are stored in a table entry, along with a pointer to the data stream that it must follow in the buffer to avoid the hazards of reading and writing data out of order.

Abstract: Provided is a system for eliminating background noise, i.e. unwanted dots of ink in the background of a document which is to be reproduced by a copier. An STS module collects statistics on a stream of pixels representing an original document generated by a scanner of the copier. The statistics are used by an MIC module to determine a reference background color value of the scanned document. The reference background color value and pixel values of pixels included in the pixel stream are compared by an RTE module and the results of comparison are used to adjust, when necessary, the pixel values remove the undesirable background noise.