Abstract: A method and apparatus for a localized printed circuit board layer extender (LLX) is provided. The apparatus relieves layer routing congestion in and around high pin count integrated circuits. The method begins when a localized layer extender is provided that is compatible with the bottom-side pin-field of a device under test (DUT). The LLX is affixed to the bottom-side pin-field of the DUT. Test signals are then routed through the LLX as part of a test procedure. The apparatus includes: a LLX that substantially matches the pin-field of a bottom side of a DUT; a LLX base; and a LLX debug interface.

Abstract: A spacer-connector and connection arrangements between daughter boards and motherboards are disclosed. Assemblies may include a daughter board one or more spacer-connectors spacing the daughter board above a motherboard and conductive elastomers providing electrical connections between the daughter board and spacer-connector and between the spacer-connector and the motherboard. The spacer-connector may include ground, power, digital and/or controlled impedance RF pathways to conduct signals between the daughter board to the mother board.

Abstract: Various socket configurations having coaxial alignment and attachments are disclosed. The various socket configurations can use two-mount and three-mount configurations to facilitate adaptability to high density routing.

Abstract: A spacer-connector and connection arrangements between daughter boards and motherboards are disclosed. Assemblies may include a daughter board one or more spacer-connectors spacing the daughter board above a motherboard and conductive elastomers providing electrical connections between the daughter board and spacer-connector and between the spacer-connector and the motherboard. The spacer-connector may include ground, power, digital and/or controlled impedance RF pathways to conduct signals between the daughter board to the mother board.

Abstract: Space transformer connectors for coupling printed circuit boards and/or other electrical connections are disclosed. A scalar design of a multilayer space transformer connector allows for a variety of pad-array field connections. A conductive elastomer interface provides for repeated and consistent coupling and decoupling of the space transformer connector.

Abstract: Various socket configurations having coaxial alignment and attachments are disclosed. The various socket configurations can use two-mount and three-mount configurations to facilitate adaptability to high density routing.

Abstract: An integrated circuit according to the present invention includes application-specific circuitry and an embedded counter assembly capable of measuring the frequency of one or more clock signals, which may be generated internally by the integrated circuit or externally by one or more sources external to the integrated circuit. The embedded counter assembly utilizes a reference clock signal having known characteristics, and measures the frequency of an unknown clock signal based upon the reference clock signal. The embedded counter assembly is capable of measuring the frequency of internal clock signals that are otherwise inaccessible via external output pins.

Abstract: An incoming serial Manchester signal is synchronously sampled by a first flip-flop with respect to a reference clock signal of a frequency f.sub.o. A second flip-flop divides the reference clock signal to provide f.sub.o /2 clocking to a pair of shift registers wherein one shift register is of bit length M and the other is of bit length N. The first flip-flop provides to the first shift register a present sample corresponding to the state of the Manchester waveform. A third flip-flop samples and stores the state of the Manchester waveform sample, as provided by the first flip-flop, which occurred one-half clock period prior to the f.sub.o /2 clocking of the shift registers. The third flip-flop provides to the second shift register a delayed sample corresponding to the state of the Manchester waveform. The sample provided to the second shift register is a sample which occurred previously in time, by 1/f.sub.o clock period, relative to the present sample provided to the first shift register.