Patents by Inventor James L. Bouknight

James L. Bouknight has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5436496
    Abstract: A vertical fuse structure including a lightly-doped shallow emitter 30 provides improved fusing characteristics. The structure includes a buried collector 14, an overlying base 30, and an emitter 44 above the base 30. In one preferred embodiment, the emitter 44 extends about 0.2 microns from the upper surface and has a dopant concentration of about 8.times.1019 atoms of arsenic per cubic centimeter at the surface. A lightly doped base region 30 extends for about 0.46 microns below the emitter 44 to the collector 14. The upper surface of emitter 44 includes a metal contact 60. Heating the metal 60/emitter 44 interface to its eutectic melting point using a current or voltage pulse causes the aluminum to short through the emitter 44 to the base 30. Shorting the emitter programs the fuse. A second preferred embodiment uses polysilicon as an interconnecting medium.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: July 25, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Rick C. Jerome, Ronald P. Kovacs, George E. Ganschow, Lawrence K. C. Lam, James L. Bouknight, Frank Marazita, Brian McFarlane, Ali Iranmanesh
  • Patent number: 5139961
    Abstract: A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.
    Type: Grant
    Filed: April 2, 1990
    Date of Patent: August 18, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Alan G. Solheim, Bamdad Bastani, James L. Bouknight, George E. Ganschow, Bancherd Delong, Rajeeva Lahri, Steve M. Leibiger, Christopher S. Blair, Rick C. Jerome, Madan Biswal, Tad Davies, Vida Ilderem, Ali A. Iranmanesh