Abstract: A communications system includes self synchronizing device sets such as telephones that are interconnected by wiring to allow communication between the devices and communication with an outside communication line, such as a subscriber telephone line provided by a central telephone company. Each individual device includes access circuitry for placing signals on the interconnecting wires so that the signals from the various devices are time division multiplexed on the same wire conductors. The individual communication sets are synchronized without the intervention of a central controller. Each set is assigned a unique identification code. Each set then listens for the identification codes placed on the interconnection wiring by the other sets and places its signal on the wiring at the proper time in response to the other detected identification codes.

Abstract: A frequency multiplexed system for coupling a plurality of individual telephone sets to at least one subscriber telephone line. The system includes a line adapter unit for controlling use of subscriber lines and for assigning the use of frequency bands to the individual telephone sets. The system includes a two-conductor interconnection cable for coupling to each of the telephone sets and to the line adapter unit. The system has a power-down mode in which the loss of external power allows each of the individual telephone sets to use the subscriber line. The line adapter unit and each of the individual telephone sets employ transconductance amplifiers so that modulated current signals are produced on the interconnection cable, thus allowing a plurality of voice signals to be summed together by voltage addition for conferencing between the telephone sets and the subscriber lines.

Abstract: The method of and circuitry for controlling the "slip" of data between input and output of a multisection memory circuit wherein the memory is used in an elastic store mode. This is accomplished by, in essence, comparing the counts of write and read counters operating with a multisection memory of at least four sections, and if the counts are too close together, such that both read and write operations could occur in the same section after advancement, then the advancing counter is not enabled for further count advancement.

Abstract: Apparatus for providing, in a multiplexed fashion, both the operations of framing to determine the position of a framing bit in a stream of data bits and, after framing has occurred, the job of providing slip control for an elastic store. Since these are essentially exclusive functions in that framing only need occur at the initial portion of a cycle and slip control need only occur after framing has been successfully completed, there is no interference between the two functions. The framing is obtained by supplying input data bits to a memory for intermediate storage and then an integral number of frames later comparing the presently received data with that received previously, and if a negative comparison occurs, eliminating that particular bit as a candidate for the framing bit. The same memory is then used along with the same addressing means for providing an elastic store along with slip control.

Abstract: A phase detector circuit for use in a phase-lock loop is illustrated wherein a voltage pump is incorporated in the phase detector circuit so as to eliminate the utilization of a comparatively high voltage power supply which is normally required to sufficiently frequency modulate the variable frequency oscillator incorporated in most phase-lock loops.

Abstract: This is a consolidated memory element allowing two simultaneously occurring independent accesses to take place. As disclosed, the apparatus contains both a random address mode and a sequential address mode to allow the simultaneous modes of (1) random read/sequential read, (2) random read/sequential write, (3) random write/sequential read.