Abstract: A high speed multiplier unit for multiplying both fixed point and floating point operands is disclosed and claimed. This multiplier unit is a system level functional unit which allows floating point and fixed point operations to be performed directly. In addition to multiplication, the multiplier unit performs exponent calculation, post-normalization, and error detection. The multiplier unit also provides for overlapped loading of operands.

Abstract: A reconfigurable parallel group of identical functional units and a method for reconfiguring this parallel grouping of identical functional units upon the occurrence of a failure by shifting the contents of the failed unit and the contents of all units between the failed unit and a spare unit one unit toward the spare unit is disclosed. A paired system of input and output busses allows control lines to activate and deactivate the appropriate busses so that a constant input output interface is maintained despite the failure provoked shift. This reconfigurable parallel group can also be stacked together to form larger configurations.