Abstract: An apparatus and method for transferring data among clients of a time division multiplexed network is provided. In one aspect of the preset invention the apparatus includes clock circuits that allow for a variable number of time slots and a variable bus cycle of the network. In another aspect of the present invention a network interface module includes an indirection register that contains relationships between memory storage locations and channels of a time domain multiplexed network. In yet another aspect of the present invention, a network interface module is provided that comprises a memory, and first and second registers. In one mode of operation of the network interface module, data from the memory for a client is pre-fetched from the memory, prior to the start of a bus cycle and is stored in the registers to minimize memory access delays in the system.

Abstract: A system for concurrent evaluation of the effect of multiple faults in a logic design being evaluated is particularly useful in the design of very large scale integrated circuits for developing a compact input test set which will permit locating a predetermined percentage of all theoretically possible fault conditions in the manufactured chips. The system includes logic evaluation hardware for simulating a given logic design and evaluating the complete operation thereof prior to committing the design to chip fabrication. In addition, and concurrently with the logic design evaluation, the system includes means for storing large number of predetermined fault conditions for each gate in the design, and for evaluating the "fault operation" for each fault condition for each gate, and comparing the corresponding results against the "good machine" operation, and storing the fault operation if different from the good operation.

Abstract: A microcode addressing system is shown which has two modes of operation for different memory search functions. The first mode, the Slow mode in which the memory operates at a standard read rate, is the mode in which the computer central processing unit performs predetermined sequential tasks in a normal fashion. The second mode of operation is the Fast mode of operation in which the memory responds to unpredetermined, dynamically changing events in the computer system at a faster than standard cycle time in order to search for and identify a particular word in central memory.