Abstract: An EPROM disclosed in this specification includes a unique floating gate memory cell which may be charged using a reduced voltage level. The memory cells are fabricated using a mask to define the buried source, drain, and field oxide regions of the memory cell. After removal of the mask, field oxide regions are formed and a floating gate is fabricated which extends beyond the boundaries of the channel region for the floating gate field effect transistor memory cell. This extended floating gate provides additional capacitive coupling between the gate/word line and the floating gate while maintaining the same capacitive coupling between the floating gate and the channel of the floating gate field effect transistor memory cell. One embodiment discloses a silicide which is applied to the buried source and drain regions. The silicide is fabricated by forming a slot through the field oxide, forming a silicide on the diffused regions, refilling the slot with an oxide, and planarizing the resulting structure.

Abstract: An EPROM disclosed in this specification includes a unique floating gate memory cell which may be charged using a reduced voltage level. The memory cells are fabricated using a mask to define the buried source, drain, and field oxide regions of the memory cell. After removal of the mask, field oxide regions are formed and a floating gate is fabricated which extends beyond the boundaries of the channel region for the floating gate field effect transistor memory cell. This extended floating gate provides additional capacitive coupling between the gate/word line and the floating gate while maintaining the same capacitive coupling between the floating gate and the channel of the floating gate field effect transistor memory cell. One embodiment discloses a silicide which is applied to the buried source and drain regions. The silicide is fabricated by forming a slot through the field oxide, forming a silicide on the diffused regions, refilling the slot with an oxide, and planarizing the resulting structure.

Abstract: A process for the fabrication of integrated circuits, wherein the interlevel dielectric material is partially etched back prior to reflow. This provides a pre-reflow profile which prevents filament problems in subsequently-patterned conductor levels, and which also avoids cracking of the interlevel dielectric during reflow.

Abstract: A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the multilevel dielectric is deposited thereover. The multilevel dielectric is removed from the capacitor area, and an oxide/nitride dielectric is deposited over the exposed bottom plate and over the multilevel by way of LPCVD. A first layer of titanium/tungsten is preferably deposited prior to contact etch, and the contacts to moat and unrelated polysilicon are formed. Metallization is sputtered overall, and the metal and titanium/tungsten are cleared to leave the metallization filling the contact holes, and a capacitor having a titanium/tungsten and metal top plate.

Abstract: A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the multilevel dielectic is deposited thereover. The multilevel dielectric is removed from the capacitor area, and an oxide/nitride dielectric is deposited over the exposed bottom plate and over the multilevel by way of LPCVD. A first layer of titanium/tungsten is preferably deposited prior to contact etch, and the contacts to moat and unrelated polysilicon are formed. Metallization is sputtered overall, and the metal and titanium/tungsten are cleared to leave the metallization filling the contact holes, and a capacitor having a titanium/tungsten and metal top plate.

Abstract: A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the multilevel dielectric is deposited thereover. The multilevel dielectric is removed from the capacitor area, and an oxide/nitride dielectric is deposited over the exposed bottom plate and over the multilevel by way of LPCVD. A first layer of titanium/tungsten is preferably deposited prior to contact etch, and the contacts to moat and unrelated polysilicon are formed. Metallization is sputtered overall, and the metal and titanium/tungsten are cleared to leave the metallization filling the contact holes, and a capacitor having a titanium/tungsten and metal top plate.

Abstract: The invention provides an integrated circuit capacitor with a silicided polysilicon electrode (which silicide has not been used as an etch stop) as a bottom plate and a metal layer as a top plate. Subsequent to the formation of a patterned polysilicon layer, a multilevel dielectric is formed, and a via is etched therethrough to a polysilicon capacitor bottom plate. Then the polysilicon bottom plate is clad with a refractory metal silicide. The capacitor dielectric is then deposited, such a dielectric preferably consisting of an oxide/nitride layered dielectric. Contacts are etched to diffusion and to polysilicon electrodes as desired, and metal is deposited and patterned to form the top electrode of the capacitor over the capacitor dielectric, and to make contact as desired to diffusion and to polysilicon. This provides an improved silicide layer in the capacitor, as compared to processes which etch through oxide down to the silicide, and thus are using the silicide as an etch stop.

Abstract: An EEPROM circuit having a word-erase capability is disclosed using buried bit line fabrication techniques. The word-erasable EEPROM uses minimum additional chip area and minimum fabrication process modification.

Abstract: EEPROM memories with crosspoint cells using buried source and drain lines plus merged floating gate transistors with floating gate coupling to control gate over the buried line insulator for high packing plus low voltage operation.

Abstract: A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the multilevel dielectric is deposited thereover. The multilevel dielectric is removed from the capacitor area, and an oxide/nitride dielectric is deposited over the exposed bottom plate and over the multilevel by way of LPCVD. A first layer of titanium/tungsten is preferably deposited prior to contact etch, and the contacts to moat and unrelated polysilicon are formed. Metallization is sputtered overall, and the metal and titanium/tungsten are cleared to leave the metallization filling the contact holes, and a capacitor having a titanium/tungsten and metal top plate.

Abstract: An EEPROM cell and array of cells is disclosed having buried diffusion source/drain lines and buried diffusion erase lines. The cells further include coupling between the floating gate and control gate above the source/drain diffusion. The disclosed cell allows high packing density and operation at low voltages.

Abstract: EEPROM memories with crosspoint cells using buried source and drain lines plus merged floating gate transistors with floating gate coupling to control gate over the buried line insulator for high packing plus low voltage operation.

Abstract: A non-volatile memory cell having a floating-gate transistor is disclosed, which has a ferroelectric material for the dielectric between the floating gate electrode and the control gate electrode. The ferroelectric material provides for non-linear capacitance characteristics with voltage, and is polarizable into two states by the application of voltage across the capacitor plates of sufficient magnitude. The memory cell is read by applying a voltage to the control gate electrode which will sufficiently be capacitively coupled to the floating gate electrode to turn on the transistor when the ferroelectric material is in the programmed state, but which will not be sufficiently coupled in the erased state to turn the transistor on. The ferroelectric material may be incorporated directly above the floating gate transistor electrode, or may be formed remotely from the transistor between two metal layers, the lower of which is connected to the floating gate electrode.

Abstract: The specification discloses a floating gate read only memory formed in an array of rows (15) and columns (17) of memory cells (10). A conductivity-type determining layer (24) is formed over a face of a semiconductor body (30). An oxide layer (32) is formed over layer (24) and spaced apart elongated trenches (44) are formed through the layers (32) and (24) to form columns (17) of impurity layers. A first gate insulating layer (32a) is formed over the trenches (44). Discrete regions of polycrystalline silicon (34) are formed over spaced apart locations of the trenches (44) to form floating gates. A second gate insulating layer (36) is formed over the floating gates. A pattern of spaced apart parallel strips (40) are formed overlying the floating gates and normal to the columns (17) to form the rows (15) of memory cells.

Abstract: An X-cell EEPROM array includes a plurality of common source regions (50) that each border on four gate regions (46), both formed at a face of a semiconductor substrate (10). Each gate region (46) further adjoins a common drain region (52). Each drain region (52) is a common drain for two EEPROM select and memory transistors. A common erase region (54) is implanted into the semiconductor layer (10) in a position remote from the source regions (50) and the drain regions (52). Four floating gate electrodes (40) extend over tunnel windows (22) that are formed on the semiconductor layer (10) in positions adjacent a single erase region (54). An integral contact (64) is made through multilevel oxide (56, 58) from a metal erase line (70) to each erase region (54).

Abstract: An integrated circuit including doubled capacitors (metal/dielectric/TiN/dielectric/polysilicon). This structure is preferably made using a patterned interlevel oxide/nitride layer to split a polycide layer, i.e. at some locations the polycide layer has low sheet resistance and at other locations the polycide layer is vertically split to provide two layers (TiN and unsilicided polysilicon), which are separated by the interlevel oxide/nitride. A double contact etch is used before the first metal interconnect layer is deposited, so that the metal makes ohmic contact to underlying silicide or silicon or TiN in some locations, and in others provides insulated metal top plates over TiN/polysilicon capacitance to provide doubled capacitors.

Abstract: A process for the fabrication of integrated circuits, wherein the interlevel dielectric material is partially etched back prior to reflow. This provides a pre-reflow profile which prevents filament problems in subsequently-patterned conductor levels, and which also avoids cracking of the interlevel dielectric during reflow.

Abstract: A non-volatile memory wherein the channel of the floating gate memory devices is recessed.

Abstract: Using a method according to one embodiment of the present invention, an EPROM array may be fabricated providing a dense EPROM array.First the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1 to 1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface.

Abstract: The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.