Patents by Inventor James L. Schafer

James L. Schafer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8165864
    Abstract: Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values from a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second set of general purpose register values on a bus.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: April 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Mullen, Marvin J. Rich, James L. Schafer
  • Publication number: 20090204796
    Abstract: Method, system and computer program product for verifying the address generation, address generation, interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values fern a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second, set of general purpose register values on a bus.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 13, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Mullen, Marvin J. Rich, James L. Schafer
  • Patent number: 7213122
    Abstract: The generation and selection of addresses to be employed in a verification environment are tightly coupled to ensure that the addresses a user desires to be selected have been generated. Addresses are generated based on one or more defined selection attributes. The generated addresses are maintained in a database structure that also includes any attributes associated with the addresses. At least one address is selected from the database structure via a filter and forwarded to a component under test.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: May 1, 2007
    Assignee: International Business Machines Corporation
    Inventors: Dean G. Bair, Edward J. Kaminski, Jr., James L. Schafer