Patents by Inventor James L. Schwartz

James L. Schwartz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5842036
    Abstract: An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: November 24, 1998
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Robert W. Martell, Michael A. Fetterman, David B. Papworth, James L. Schwartz
  • Patent number: 5809325
    Abstract: An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: September 15, 1998
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Robert W. Martell, Michael A. Fetterman, David B. Papworth, James L. Schwartz
  • Patent number: 5555432
    Abstract: An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution.
    Type: Grant
    Filed: August 19, 1994
    Date of Patent: September 10, 1996
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Robert W. Martell, Michael A. Fetterman, David B. Papworth, James L. Schwartz