Abstract: Systems and methods for codependent physical unclonable function (PUF)/random number generator (RNG) generator pairing for physical provenance are described herein. In one example a device includes physical unclonable function (PUF) circuitry configured to produce a PUF output in response to an input and random number generator (RNG) circuitry configured to output one or more random numbers. The PUF circuitry and the RNG circuitry share one or more components such that an alteration of the RNG circuitry alters the PUF circuitry. The device is configured to determine whether the RNG circuitry is an untainted source of random numbers based on an output of the PUF circuitry.

Abstract: Systems and methods for an active transistor RNG circuit with MEMS entropy are described herein. In one example, an RNG circuit includes one or more MEMS structures configured to provide an output, wherein the output includes active oscillations, charge, resistance, capacitance, and/or inductance values. The RNG circuit further includes active transistor RNG circuitry communicatively coupled to the one or more MEMS structures. The active transistor RNG circuitry is configured to generate a random number output based on the output by the one or more MEMS structures. The random number output generated by the active transistor RNG circuitry is an output of the RNG circuit.

Abstract: Systems and methods for an active transistor PUF circuit with MEMS uniqueness are described herein. In one example, a PUF circuit includes one or more MEMS structures configured to provide an output, wherein the output includes active oscillations, charge, resistance, inductance, and/or capacitance values. The PUF circuit further includes active transistor PUF circuitry communicatively coupled to the one or more MEMS structures. The active transistor PUF circuitry is configured to receive a challenge input and generate a PUF response in response to the challenge input. The PUF response is generated based on the output provided by the one or more MEMS structures and manufacturing variation in components of the active transistor PUF circuitry. The PUF response generated by the active transistor PUF circuitry is an output of the PUF circuit.

Abstract: A system is provided. The system includes a physical unclonable function (PUF) circuit having an input, an output and an embedded microelectromechanical system (MEMS) device; and an interface, coupled to the PUF circuit, and being configured to be coupled to a mechanical structure; wherein the embedded MEMS device is configured to detect a parameter or characteristic associated with the mechanical structure and to provide an input to the PUF circuit based on the detected parameter, whereby the PUF circuit uses the input from the embedded MEMS device to extend trust to the mechanical structure.

Abstract: A system that includes: a microelectromechanical system (MEMS) device for generating an output signal at an output of the MEMS device, the MEMS device receiving at least one input signal at an input of the MEMS device; a storage medium configured to store a signal injection function and an output generation function; and a processor, in communication with the MEMS device and the storage medium, the processor configured to run the signal injection function to selectively modify the at least one input signal to produce a modified input signal and to provide the modified input signal to the input of the MEMS device, and that is configured to run an output generation function to extract a random component and a unique component from the output signal, wherein the random component and the unique component are generated by the MEMS device based on the modified at least one input signal.

Abstract: A computer readable storage medium and techniques to verify that information stored in the storage medium is accurate. Information in the storage medium is accurate when it is the same as the information written to the storage medium. In some examples, circuitry of the computer readable storage medium may be subject to charge leakage, and one or more bits of a word stored in the storage medium may decay, for example, from a logic zero to a logic one. The computer readable storage medium of this disclosure, e.g., referred to as a memory for short, may employ bitwise word redundancy, and selective bit wise code inversion to identify and correct errors in the stored information.

Abstract: A semiconductor assembly including: a first semiconductor having a plurality of electrical contacts extending from an upper surface of the first semiconductor; a second semiconductor adjacent to the first semiconductor; and a mesh disposed between and affixed to the upper surface of the first semiconductor and the lower surface of the second semiconductor. A lower surface of the second semiconductor is electrically connected to the first semiconductor via the plurality of electrical contacts. The mesh comprises a plurality of interconnecting struts defining a plurality of openings, wherein the plurality of openings is configured to receive the plurality of electrical contacts.

Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Abstract: In some examples, a programmable device may load configuration data into a configuration storage to configure programmable logic of the programmable device. The programmable device may include a key generation logic that may read at least a portion of the configuration data from the configuration storage. The key generation logic may generate a cryptographic key based at least in part on the at least a portion of the configuration data read from the configuration storage.

Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Abstract: A circuit package for electrically connecting a plurality of modules. The circuit package having a first and second mounting plate, each including a plurality of module connectors configured to receive and form electrical connections with the plurality of modules. The circuit package also having a first and second sidewall mounted to the first and second mounting plates. The first sidewall including a plurality of sidewall fins extending outward from the first sidewall so that the plurality of sidewall fins are positioned between the first and second mounting plates and at least partially interleave with the plurality of modules.

Abstract: A system may encrypt the contents of a memory using an encryption key that is generated based on an entropy-based key derivation function. The system may generate a random value as a key split associated with an instance of writing data to memory. The system may generate an encryption key for encrypting the data using an entropy-based key derivation function based at least in part on the key split. The system may encrypt the data using the encryption key. The system may store the encrypted data and the key split to the memory.

Abstract: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.

Abstract: In some examples, a programmable device may load configuration data into a configuration storage to configure programmable logic of the programmable device. The programmable device may include a key generation logic that may read at least a portion of the configuration data from the configuration storage. The key generation logic may generate a cryptographic key based at least in part on the at least a portion of the configuration data read from the configuration storage.

Abstract: In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer.

Abstract: A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.