Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

Abstract: A DAC may include a decoder configured to receive a digital input signal, and first and second sub-DACs coupled in parallel to the decoder, each of the first and second sub-DACs having first and second LSB banks, and an MSB bank coupled between the first and second LSB banks. The decoder may be configured to selectively control the first and second LSB banks, and the MSB bank based upon the digital input signal. The DAC may include an output network coupled to the first and second sub-DACs and configured to generate an analog output signal related to the digital input signal.

Abstract: A DAC may include a decoder configured to receive a digital input signal, and first and second sub-DACs coupled in parallel to the decoder, each of the first and second sub-DACs having first and second LSB banks, and an MSB bank coupled between the first and second LSB banks. The decoder may be configured to selectively control the first and second LSB banks, and the MSB bank based upon the digital input signal. The DAC may include an output network coupled to the first and second sub-DACs and configured to generate an analog output signal related to the digital input signal.

Abstract: A sense amplifier for use in memory devices. The sense amplifier may include a pair of cross-coupled inverters, each inverter including at least two transistors. The sense amplifier may further include a first capacitor coupled to a first input/output terminal of the sense amplifier and a second capacitor coupled to a second input/output terminal thereof. A change in voltage differential appearing across the input/output terminals bootstraps the cross-coupled inverters to facilitate activation and deactivation of the transistors in the cross-coupled inverters. Consequently, response time of the sense amplifier is reduced.

Abstract: A sense amplifier for use in memory devices. The sense amplifier may include a pair of cross-coupled inverters, each inverter including at least two transistors. The sense amplifier may further include a first capacitor coupled to a first input/output terminal of the sense amplifier and a second capacitor coupled to a second input/output terminal thereof. A change in voltage differential appearing across the input/output terminals bootstraps the cross-coupled inverters to facilitate activation and deactivation of the transistors in the cross-coupled inverters. Consequently, response time of the sense amplifier is reduced.

Abstract: A dynamic random access memory (DRAM) device is disclosed. The DRAM device includes a memory cell array having a twisted bit line architecture. The memory cell array includes at least one pair of redundant rows of memory cells. Redundant row decode circuitry is capable of configuring the pair of redundant rows to replace any one row of memory cells having a defect. Each pair of bit lines is coupled to a distinct memory cell from each redundant row of the redundant row pair so that both the true and complement version of a data value is maintained by the redundant row pair. Rows of reference cells are disconnected and/or disabled during a memory access operation involving the redundant row pair. The use of a pair of redundant rows of memory cells to replace a single row of memory cells having a defect substantially reduces the complexity of decode circuitry for enabling the rows of reference cells.

Abstract: A bit line recovery circuit for random access memory. The circuit includes a pair of pull-up devices, each of which is connected to a bit line of a bit line pair. Pass gates are disposed between a sense amplifier and the bit lines. The pull-up devices are cross-coupled such that the gate node of the pull-up devices are connected to the sense amplifier on the opposed side of the pass gates in order to rapidly turn on the appropriate pull-up device following a memory cell read operation.

Abstract: The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over a portion of a substrate wherein the first transistor has a gate electrode and a source and drain regions. First and second interconnect regions are formed over a portion of the gate electrode and a portion of the source and drain regions of the first transistor, respectively. A source and drain region of a second transistor is formed over the second interconnect. A Vcc conductive layer is formed over a portion of the source and drain region of the second transistor which is formed over the second interconnect.

Abstract: A relatively large number of test fixtures are provided for an available tester. The tester is programmed to access the individual test fixtures independently, and does so only when the devices connected to them are to be tested. When the test fixtures are not in such a test mode, local power sources provided for each fixture are used to apply stress voltages to the devices being tested. This frees the tester from the requirement for providing stressing voltages to the devices, allowing it to be efficiently used to perform testing on a larger number of devices concurrently.