Abstract: A system includes a bus, a processor operably coupled to the bus, a memory operably coupled to the bus, a plurality of input/output (I/O) devices operably coupled to the bus, where each of the I/O devices has a set of control registers, and a first shared I/O unit operably coupled to the bus. The first shared I/O unit has a plurality of shared functions and is configured to perform the shared functions, where the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit.

Abstract: Methods and systems are provided for managing thread execution in a processor. Multiple instructions are fetched from fetch queues. The instructions satisfy the condition that they involve fewer bits than the integer processing pathway that is used to execute them. The instructions are decoded, and divided into groups. The instructions are processed simultaneously through the pathway, such that part of the pathway is used to execute one group of instructions and another part of the pathway is used to execute another group of instructions. These parts are isolated from one another so the execution of the instructions can share the pathway and execute simultaneously and independently.

Abstract: A system includes a bus, a processor operably coupled to the bus, a memory operably coupled to the bus, a plurality of input/output (I/O) devices operably coupled to the bus, where each of the I/O devices has a set of control registers, and a first shared I/O unit operably coupled to the bus. The first shared I/O unit has a plurality of shared functions and is configured to perform the shared functions, where the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit.

Abstract: A multi-thread processor including a processing core. The processing core including multiple threads and a scheduler. The scheduler includes a thread state register. The thread state register being capable of storing a selective wait state for a selected one of the threads. A method of scheduling threads in a multi-thread processor is also disclosed.