Abstract: A processor is provided for calculating an output pointer to a first data item by combination of an input pointer to a second data item with an offset. The processor includes logic for generating, in a single operation, a zero value for the output pointer when the input pointer is zero and an output pointer value calculated as the offset value added to, or subtracted from, the input pointer value when the input pointer is non-zero.

Abstract: An improved cache memory and method of operation thereof. The cache memory includes a doubly-linked loop of cache lines and a single pointer operable to address a cache line in the doubly-linked loop. In the cache memory, the pointer is preferably operable to address a next cache line in the doubly-linked loop, or a previous cache line in the doubly-linked loop. The cache memory as described permits a reduction in the number of instruction steps involved in controlling the cache lines. The improved cache memory may be implemented in a data processing system or within a computer program product.

Abstract: An information processing system includes a plurality of different hardware component types (e.g. interface chip, chip port and chip port DMA channel hardware). The chip may include for example two chip ports, each of which includes twelve DMA channels. The system further includes software for controlling the operation of the hardware, the software providing a software class for each hardware type. Each software class defines a constructor for creating instances of each class, one instance for each member of the type e.g. twelve instances of the chip port DMA class. The constructor further includes or references test code for testing each type member. Thus, on construction of each instance of the chip port DMA class, the associated constructor tests the operation of the DMA channel. If there is a failure, the constructor throws an exception to the chip port constructor which then determines how to handle the error.