Abstract: Aspects relate to techniques for controlling signal voltage levels across a wired data link for data communication between apparatuses. A first device can advertise multiple supported signal voltage levels to a peer device connected by the wired data link. The devices can implement the same signal voltage level(s) or different signal voltage levels. The peer devices can compare and select a compatible signal voltage level for data communication. The first device can provide a signal voltage indication signal that is configurable to a plurality of voltage levels corresponding to a plurality of signal voltages. At least one of the plurality of voltage levels can indicate that the first device can operate the data link at a plurality of signal voltages. In some examples, the wired data link can be a peripheral component interconnect express (PCIe) link.

Abstract: Thermal mitigation features may be included in a Universal Serial Bus (USB) cable assembly or in the USB receptacle portion of a device. In one aspect, one or both ends of a USB cable jacket may have greater thermal conductivity than the portion between them. The portion having the greater thermal conductivity may dissipate excess heat from the cable into the environment. In another aspect, a USB cable connector or the USB receptacle portion of a device may include a thermoelectric heat pump. The thermoelectric heat pump may move excess heat from the cable assembly or receptacle into a portion of the cable assembly or device that dissipates the heat into the environment.

Abstract: Alternate sideband signaling in a Peripheral Component Interconnect (PCI) express (PCIE) link may be enabled over existing sideband lines in a conventional PCIE link. For example, the default sideband communication of PCIE may be changed to a Universal Asynchronous receiver/transmitter (UART), line multiplex UART (LM-UART), serial peripheral interface (SPI), I2C, or I3C mode of communication. This change may be negotiated between the host and slave of the communication link, with a transition occurring after the negotiation concludes. The new mode of communication may include or encode the conventional PCIE sideband signals.

Abstract: Thermal mitigation features may be included in a Universal Serial Bus (USB) cable assembly or in the USB receptacle portion of a device. In one aspect, one or both ends of a USB cable jacket may have greater thermal conductivity than the portion between them. The portion having the greater thermal conductivity may dissipate excess heat from the cable into the environment. In another aspect, a USB cable connector or the USB receptacle portion of a device may include a thermoelectric heat pump. The thermoelectric heat pump may move excess heat from the cable assembly or receptacle into a portion of the cable assembly or device that dissipates the heat into the environment.

Abstract: Alternate sideband signaling in a Peripheral Component Interconnect (PCI) express (PCIE) link may be enabled over existing sideband lines in a conventional PCIE link. For example, the default sideband communication of PCIE may be changed to a Universal Asynchronous receiver/transmitter (UART), line multiplex UART (LM-UART), serial peripheral interface (SPI), I2C, or I3C mode of communication. This change may be negotiated between the host and slave of the communication link, with a transition occurring after the negotiation concludes. The new mode of communication may include or encode the conventional PCIE sideband signals.

Abstract: Thermal mitigation features may be included in a Universal Serial Bus (USB) cable assembly or in the USB receptacle portion of a device. In one aspect, one or both ends of a USB cable jacket may have greater thermal conductivity than the portion between them. The portion having the greater thermal conductivity may dissipate excess heat from the cable into the environment. In another aspect, a USB cable connector or the USB receptacle portion of a device may include a thermoelectric heat pump. The thermoelectric heat pump may move excess heat from the cable assembly or receptacle into a portion of the cable assembly or device that dissipates the heat into the environment.

Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

Abstract: Security techniques for a Peripheral Component Interconnect (PCI) express (PCIE) system include a transport layer protocol (TLP) packet that has a prepended TLP prefix indicating the security features of the TLP packet and an integrity check value (ICV) appended to the TLP packet. The ICV is based on the TLP packet and any TLP prefixes including a security prefix. At a receiver, if the ICV does not match, then the receiver has evidence that the TLP packet may have been subjected to tampering. Further, the TLP packet may be encrypted to prevent snooping, and this feature would be indicated in the TLP prefix. Still further, the TLP prefix may include a counter that may be used to prevent replay attacks. PCIE contemplates flexible TLP prefixes, and thus, the standard readily accommodates the addition of a TLP prefix which indicates the security features of the TLP packet.

Abstract: Fast invalidation in peripheral component interconnect (PCI) express (PCIe) address translation services (ATS) initially utilize a fast invalidation request to alert endpoints that an address is being invalidated with a fast invalidation synchronization command that causes the endpoints to flush through any residual read/write commands associated with any invalidated address and delete any associated address entries in an address translation cache (ATC). Each endpoint may send a synchronization complete acknowledgement to the host. Further, a tag having an incrementing identifier for each invalidation request may be used to determine if an endpoint has missed an invalidation request.

Abstract: Fast invalidation in peripheral component interconnect (PCI) express (PCIe) address translation services (ATS) initially utilize a fast invalidation request to alert endpoints that an address is being invalidated with a fast invalidation synchronization command that causes the endpoints to flush through any residual read/write commands associated with any invalidated address and delete any associated address entries in an address translation cache (ATC). Each endpoint may send a synchronization complete acknowledgement to the host. Further, a tag having an incrementing identifier for each invalidation request may be used to determine if an endpoint has missed an invalidation request.

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

Abstract: A hybrid virtual general purpose input/output (VGI) architecture is provided including a pair of devices coupled through a high-speed cable. The architecture enables a device to communicate sideband signals through the high-speed cable using two pins coupled to respective interconnects of a bus. In an aspect, the architecture may implement link selection without protocol consolidation where the device may configure the two pins for I2C (or I3C) signaling or VGI signaling. In another aspect, the architecture may implement link bridging with protocol consolidation where the device may transmit (or receive) I2C (or I3C) signals through the high-speed cable using a VGI communication protocol.

Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.

Abstract: System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a bit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message. Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

Abstract: A dual-data-rate interface is provided that includes a transmitter driving a transmit pin coupled to a receive pin of a receiver. The receiver drives its receive pin with cycles of a fetch clock. The transmitter responds to each edge of the fetch clock by transmitting a bit over the transmit pin to the receiver.

Abstract: A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.