Patents by Inventor James Loran Ball

James Loran Ball has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processors operable to allow flexible instruction alignment
    Patent number: 9740488
    Abstract: Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 22, 2017
    Assignee: Altera Corporation
    Inventor: James Loran Ball
  • PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT
    Publication number: 20150032995
    Abstract: Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.
    Type: Application
    Filed: October 15, 2014
    Publication date: January 29, 2015
    Applicant: Altera Corporation
    Inventor: James Loran Ball
  • Processors operable to allow flexible instruction alignment
    Patent number: 8874881
    Abstract: Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: October 28, 2014
    Assignee: Altera Corporation
    Inventor: James Loran Ball
  • Method and apparatus for performing trace data compression
    Patent number: 8250542
    Abstract: A method for compressing trace data includes maintaining a record of register values known to a debugger unit. A data packet is generated that includes a value in response to determining that the debugger unit is unable to determine the value from the register values known to the debugger unit.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: August 21, 2012
    Assignee: Altera Corporation
    Inventor: James Loran Ball
  • PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT
    Publication number: 20110314265
    Abstract: Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 22, 2011
    Applicant: ALTERA CORPORATION
    Inventor: James Loran Ball
  • Processors operable to allow flexible instruction alignment
    Patent number: 8006071
    Abstract: Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 23, 2011
    Assignee: Altera Corporation
    Inventor: James Loran Ball
  • Modular processor debug core connection for programmable chip systems
    Patent number: 7627784
    Abstract: Methods and apparatus are provided for implementing a semiconductor device with a debug core separate from a processor core. The user configurable debug core can be customized to include one or more debug core submodules. Each debug core submodule is generally associated with a particular debug feature such as trace generation, performance counters, or hardware triggers. The debug core can be driven through a variety of interfaces to allow debugging, monitoring, and control of processor operations.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: December 1, 2009
    Assignee: Altera Corporation
    Inventors: Timothy P. Allen, Sean R. Atsatt, James Loran Ball
  • Invalidation of instruction cache line during reset handling
    Patent number: 7203799
    Abstract: Methods and apparatus are provided for handling events such as faults and resets. Specialized circuitry or hardware is provided within a processor to invalidate the cache line associated with the processor cache reset address. Based on the invalided state of the cache reset address line, the processor obtains new instructions from data memory. The new instructions can be configured to invalidate the remaining cache lines using software mechanisms.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: April 10, 2007
    Assignee: Altera Corporation
    Inventor: James Loran Ball