Abstract: In one embodiment, a power on reset circuit includes a main circuit and a translation circuit. The main circuit may be configured to receive an external signal and to generate an input signal that is indicative of a state of the external signal. The translation circuit may be configured to receive the input signal and provide a power on reset signal indicative of a brownout condition of the external signal. The external signal may be a relatively high voltage signal compared to the power on reset signal.

Abstract: The invention relates to a voltage reference source used to control an overvoltage tolerant input/output buffer for a mixed voltage bus system. The voltage source comprises a voltage tracking circuit having a first input receiving a variable voltage. and a second input receiving a reference voltage. the voltage tracking circuit being adapted to generate an output voltage in response to the difference between the variable voltage and the reference voltage. wherein where the variable voltage is less than the reference voltage. the output voltage is held at substantially zero volts. When the variable voltage exceeds the reference voltage. the output tracks the voltage at the variable voltage input.

Abstract: The invention relates to a voltage reference source used to control an overvoltage tolerant input/output buffer for a mixed voltage bus system. The voltage source comprises a voltage tracking circuit having a first input receiving a variable voltage, and a second input receiving a reference voltage, the voltage tracking circuit being adapted to generate an output voltage in response to the difference between the variable voltage and the reference voltage, wherein where the variable voltage is less than the reference voltage, the output voltage is held at substantially zero volts. When the variable voltage exceeds the reference voltage, the output tracks the voltage at the variable voltage input.

Abstract: An electrostatic discharge (ESD) protection circuit for an output transistor coupled to an I/O pin of an integrated circuit, including a logic circuit having at least one data input, a tristate enable input, and an tristate output coupled to a gate node of the output transistor wherein the tristate output is placed in a high impedance state in response to the tristate enable input. The ESD protection circuit also includes a tristate enable circuit which drives the tristate enable input according to the presence or absence of an ESD event on the I/O pin. During normal operation, the tristate enable circuit applies a first logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a low impedance state, and during an ESD event on the I/O pin, the tristate enable circuit applies a second logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a high impedance state.

Abstract: The invention relates to a mixed voltage bus system and in particular, interfaces between a number of integrated circuits and a bus where some of the integrated circuits operate at one logic level and others operate at a different logic level. An overvoltage tolerant interface for a semiconductor integrated device particulary useful in such a system may contain a pad, a pull-up transistor coupled to the pad, a voltage supply having an operating voltage, and an isolation switch operative to isolate the pull-up transistor from the voltage supply when a voltage at the pad exceeds the operating voltage of the voltage supply.