Patents by Inventor James M. Aufiero

James M. Aufiero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9479255
    Abstract: An optical network terminal is provided for use in a passive optical network (PON). The optical network terminal includes a data port for receiving data packets from an external device and a processor for converting the data packets to data link frames. In addition, the optical network terminal includes a memory configured to store a time division multiplexing scheme identifying a time slot assigned to each of a plurality of network nodes in the PON for transmission of upstream optical signals. An optical transceiver is provided for converting the data link frames to upstream optical signals and transmitting the optical signals on an upstream TDMA (time division, multiple access) channel to an Optical Line Terminal (OLT). The optical transceiver includes a burst mode laser diode for generating the optical signals and a burst mode laser driver for biasing the laser diode with a bias signal and a modulation bias signal. The laser driver includes a dual closed loop feedback control circuit.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: October 25, 2016
    Assignee: ARRIS Enterprises, Inc.
    Inventors: David B. Bowler, James M. Aufiero, Francis J. Calabresi, Christopher J. Pekalsky
  • Publication number: 20090310961
    Abstract: A method is provided to calibrate a monitor photodiode that measures the optical output power generated by an optoelectronic transceiver module that includes a burst mode laser diode. The method includes disabling the power control loop that controls an average optical output power generated by the laser diode during a laser burst. A series of logic zero signals is applied to a data input of the transceiver module and the logic zero level of the optical signal generated by the burst mode laser diode while applying the series of logic zero signals is measured. The logic zero bias level applied to the laser diode is adjusted until the measured logic zero level of the optical signal reaches a first desired value. While maintaining the optical signal at the first desired value, a first value of a current generated by the monitor photodiode in response to optical energy received from a back facet of the laser diode is stored.
    Type: Application
    Filed: June 13, 2008
    Publication date: December 17, 2009
    Applicant: GENERAL INSTRUMENT CORPORATION
    Inventors: David B. Bowler, James M. Aufiero, Francis J. Calabresi, Christopher J. Pekalsky, Jason G. Luk
  • Publication number: 20090274471
    Abstract: An optical network terminal is provided for use in a passive optical network (PON). The optical network terminal includes a data port for receiving data packets from an external device and a processor for converting the data packets to data link frames. In addition, the optical network terminal includes a memory configured to store a time division multiplexing scheme identifying a time slot assigned to each of a plurality of network nodes in the PON for transmission of upstream optical signals. An optical transceiver is provided for converting the data link frames to upstream optical signals and transmitting the optical signals on an upstream TDMA (time division, multiple access) channel to an Optical Line Terminal (OLT). The optical transceiver includes a burst mode laser diode for generating the optical signals and a burst mode laser driver for biasing the laser diode with a bias signal and a modulation bias signal. The laser driver includes a dual closed loop feedback control circuit.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 5, 2009
    Applicant: GENERAL INSTRUMENT CORPORATION
    Inventors: David B. Bowler, James M. Aufiero, Francis J. Calabresi, Christopher J. Pekalsky
  • Patent number: 4730212
    Abstract: A fluoroscopic image is processed digitally using a television camera operating at a frame rate of at least 30 frames per second viewing the image and providing an analog video output, a digitizer which digitizes the analog video output to provide digital information representative of the analog signal, a plurality of frame processors which carry out arithmetic and logical operations on the digital image information and are operable at the frame rate of the television camera coupled to the output of the digitizer, a 2-D filter operable at the frame rate of the television camera coupled to said frame processors, a converter and interface to convert digital image information processed in the frame processors and 2-D filter back into an analog signal and television display coupled to the output of the converter for displaying the processed signal.
    Type: Grant
    Filed: January 16, 1987
    Date of Patent: March 8, 1988
    Assignee: ITEK Corporation
    Inventors: David R. Wojcik, Richard J. Jones, James M. Aufiero
  • Patent number: 4710966
    Abstract: A plurality of digital words representing picture elements are sequentially loaded into a readin register, which words are thereafter written in parallel into a random access memory via a write data register. The words are subsequently readout of the random access memory in parallel into a read data register and to a readout data register which thereafter sequentially transmits the words stored therein to an output circuit. The arrangement is such that each word may flow through the pipeline to be processed during a clock period of P ns; although the RAM response time is greater than P ns.
    Type: Grant
    Filed: November 12, 1986
    Date of Patent: December 1, 1987
    Assignee: Itek Corporation
    Inventor: James M. Aufiero
  • Patent number: 4680628
    Abstract: A fluoroscopic image is processed digitally using a television camera operating at a frame rate of at least 30 frames per second viewing the image and providing an analog video output, a digitizer which digitizes the analog video output to provide digital information representative of the analog signal, a plurality of frame processors which carry out arithmetic and logical operations on the digital image information and are operable at the frame rate of the television camera coupled to the output of the digitizer, a 2-D filter operable at the frame rate of the television camera coupled to said frame processors, a converter and interface to convert digital image information processed in the frame processors and 2-D filter back into an analog signal and television display coupled to the output of the converter for displaying the processed signal.
    Type: Grant
    Filed: January 4, 1984
    Date of Patent: July 14, 1987
    Assignee: Itek Corporation
    Inventors: David R. Wojcik, Richard J. Jones, James M. Aufiero
  • Patent number: 4532546
    Abstract: Circuitry for converting interlaced video data to non-interlaced video data at 30 frames per second, real time video rate, where rows of successive lines of video data applied to a single frame memory are provided having data control means including readin and readout means for initially sequentially loading each row of memory with lines of interlaced video data of the first frame sequentially applied to the memory and thereafter reading out successive memory rows of the first frame from memory, while replacing each line readout by whatever line of the second frame is applied to memory in real time just after readout, until all lines of data of the second frame are inserted into memory.
    Type: Grant
    Filed: January 4, 1984
    Date of Patent: July 30, 1985
    Assignee: Itek Corporation
    Inventors: James M. Aufiero, William P. D'Agostino, Jr., John P. Moore