Patents by Inventor James M. Blackwell
James M. Blackwell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953826Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.Type: GrantFiled: September 1, 2021Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: James M. Blackwell, Robert L. Bristol, Marie Krysak, Florian Gstrein, Eungnak Han, Kevin L. Lin, Rami Hourani, Shane M. Harlson
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Patent number: 11955343Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.Type: GrantFiled: March 22, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Robert L. Bristol, Marie Krysak, James M. Blackwell, Florian Gstrein, Kent N. Frasure
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Patent number: 11955377Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.Type: GrantFiled: January 4, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Kevin L. Lin, Robert L Bristol, James M. Blackwell, Rami Hourani, Marie Krysak
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Publication number: 20240071917Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.Type: ApplicationFiled: October 27, 2023Publication date: February 29, 2024Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
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Patent number: 11874600Abstract: A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.Type: GrantFiled: April 4, 2022Date of Patent: January 16, 2024Assignee: Intel CorporationInventors: Marie Krysak, James M. Blackwell, Robert L. Bristol, Florian Gstrein
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Patent number: 11854787Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.Type: GrantFiled: May 2, 2022Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Richard E. Schenker, Robert L. Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A. Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
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Publication number: 20220352068Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: ApplicationFiled: June 15, 2022Publication date: November 3, 2022Applicant: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Patent number: 11444024Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: GrantFiled: November 2, 2020Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Publication number: 20220262722Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
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Patent number: 11406972Abstract: Catalysts for facilitating cross-linking of liquid precursors into solid dielectric materials are disclosed. Initially, catalysts are protected, either by coordination with other compounds or by conversion to an ionic salt. Protection prevents catalysts from facilitating cross-linking unless activated. A catalyst is activated upon receiving an excitation, e.g. thermal excitation by heating. Upon receiving an excitation, protection of a catalyst dissociates, decomposes, becomes neutralized, or is otherwise transformed to allow the catalyst to facilitate cross-linking of the precursors into solid dielectric materials. Methods for fabricating dielectric materials using such protected catalysts as well as devices comprising the resulting materials are also described. Dielectric materials comprising cross-linked cyclic carbosilane units having a ring structure including C and Si may be formed in this manner.Type: GrantFiled: December 4, 2015Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: James M. Blackwell, David J. Michalak, Jessica M. Torres, Marie Krysak, Jeffery D. Bielefeld
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Publication number: 20220229364Abstract: A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Marie KRYSAK, James M. BLACKWELL, Robert L. BRISTOL, Florian GSTREIN
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Publication number: 20220216065Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.Type: ApplicationFiled: March 22, 2022Publication date: July 7, 2022Inventors: Robert L. BRISTOL, Marie KRYSAK, James M. BLACKWELL, Florian GSTREIN, Kent N. FRASURE
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Patent number: 11373950Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.Type: GrantFiled: December 2, 2020Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Richard E. Schenker, Robert L. Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A. Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
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Publication number: 20220139823Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: ApplicationFiled: November 2, 2020Publication date: May 5, 2022Applicant: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Publication number: 20220139772Abstract: Integrated circuit interconnect structures including an interconnect metallization feature with a liner material of a greater thickness between a fill metal and dielectric material, and of a lesser thickness between the fill metal and a lower-level interconnect metallization feature. The liner material may be substantially absent from an interface between the fill metal and the lower-level interconnect metallization feature. Liner material of reduced thickness at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive liner material that may enhance the scalability of interconnect structures. In some embodiments, liner material is deposited upon dielectric surfaces with an area selective atomic layer deposition process. For single damascene implementations, both a via and a metal line may include a selectively deposited liner material.Type: ApplicationFiled: November 2, 2020Publication date: May 5, 2022Applicant: Intel CorporationInventors: Christoper Jezewski, Jiun-Ruey Chen, Miriam Reshotko, James M. Blackwell, Matthew Metz, Che-Yun Lin
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Patent number: 11320734Abstract: A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.Type: GrantFiled: September 30, 2016Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: Marie Krysak, James M. Blackwell, Robert L. Bristol, Florian Gstrein
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Publication number: 20220130719Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.Type: ApplicationFiled: January 4, 2022Publication date: April 28, 2022Inventors: Kevin L. LIN, Robert L. BRISTOL, James M. BLACKWELL, Rami HOURANI, Marie KRYSAK
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Patent number: 11315798Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.Type: GrantFiled: April 8, 2016Date of Patent: April 26, 2022Assignee: Intel CorporationInventors: Robert L. Bristol, Marie Krysak, James M. Blackwell, Florian Gstrein, Kent N. Frasure
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Publication number: 20220102207Abstract: Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Inventors: Florian GSTREIN, Rami HOURANI, Gopinath BHIMARASETTI, James M. BLACKWELL
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Patent number: 11251072Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.Type: GrantFiled: December 23, 2016Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Kevin L. Lin, Robert L. Bristol, James M. Blackwell, Rami Hourani, Marie Krysak