Abstract: A method for facilitating adaptive frequency in a processor having a plurality of cores. The method can include conducting tests on the processor; determining, via the processor testing system, default parameters for operating one or more of the cores, wherein the default parameters are based on results of the tests and cause one or more of the cores to operate within production yield goals of the processor; determining alternative parameters for operating one or more of the cores, wherein the alternative parameters are based on results of the test and cause one or more of the cores to operate outside production yield goals of the processor, and wherein the alternative parameters are usable to reconfigure one or more of the cores after an initial operation per the default parameters; and writing the default parameters and the alternative parameters to a production data storage of the processor.

Abstract: A method for facilitating adaptive frequency in a processor having a plurality of cores. The method can include conducting tests on the processor; determining, via the processor testing system, default parameters for operating one or more of the cores, wherein the default parameters are based on results of the tests and cause one or more of the cores to operate within production yield goals of the processor; determining alternative parameters for operating one or more of the cores, wherein the alternative parameters are based on results of the test and cause one or more of the cores to operate outside production yield goals of the processor, and wherein the alternative parameters are usable to reconfigure one or more of the cores after an initial operation per the default parameters; and writing the default parameters and the alternative parameters to a production data storage of the processor.

Abstract: A processor can have a plurality of cores. A first core processor of a first core can read one or more values of a default parameter set. The first core can be operated in accordance with a first operating characteristic based, at least in part, on the one or more values of the default parameter set. The first core processor can receive an indication to change the operating characteristic of the first core processor. In response to receiving the indication to change the operating characteristic, a signal can be issued to the first core processor to reset. In response to the reset, the first core processor can read one or more values of an alternative parameter set. The first core processor can then be operated in accordance with a second operating characteristic based, at least in part, on the one or more values of the alternative parameter set.

Abstract: A processor can have a plurality of cores. A first core processor of a first core can read one or more values of a default parameter set. The first core can be operated in accordance with a first operating characteristic based, at least in part, on the one or more values of the default parameter set. The first core processor can receive an indication to change the operating characteristic of the first core processor. In response to receiving the indication to change the operating characteristic, a signal can be issued to the first core processor to reset. In response to the reset, the first core processor can read one or more values of an alternative parameter set. The first core processor can then be operated in accordance with a second operating characteristic based, at least in part, on the one or more values of the alternative parameter set.

Abstract: System and method using low voltage current measurements to measure voltage network currents in an integrated circuit (IC). In one aspect, a low voltage current leakage test is applied voltage networks for the IC or microchip via one or more IC chip connectors. One or multiple specifications are developed based on chip's circuit delay wherein a chip is aborted or sorted into a lesser reliability sort depending whether the chip fails specification. Alternately, a low voltage current leakage test begins an integrated circuit test flow. Then there is run a high voltage stress, and a second low voltage current leakage test is thereafter added. Then, there is compared the second low voltage test to the first low V test, and if the measured current is less on second test, this is indicative of a defect present which may result in either a scrap or downgrade reliability of chip.

Abstract: Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.

Abstract: System and method using low voltage current measurements to measure voltage network currents in an integrated circuit (IC). In one aspect, a low voltage current leakage test is applied voltage networks for the IC or microchip via one or more IC chip connectors. One or multiple specifications are developed based on chip's circuit delay wherein a chip is aborted or sorted into a lesser reliability sort depending whether the chip fails specification. Alternately, a low voltage current leakage test begins an integrated circuit test flow. Then there is run a high voltage stress, and a second low voltage current leakage test is thereafter added. Then, there is compared the second low voltage test to the first low V test, and if the measured current is less on second test, this is indicative of a defect present which may result in either a scrap or downgrade reliability of chip.

Abstract: A method of calibrating a thermal sensor includes setting a wafer to a control temperature. The wafer includes the thermal sensor and other chip logic. The method also includes applying power exclusively to a thermal sensor circuit, calibrating the thermal sensor, and storing a calibration result. The method also includes retrieving the calibration result upon application of power to the other chip logic.

Abstract: Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.

Abstract: A method of calibrating a thermal sensor includes setting a wafer to a control temperature. The wafer includes the thermal sensor and other chip logic. The method also includes applying power exclusively to a thermal sensor circuit, calibrating the thermal sensor, and storing a calibration result. The method also includes retrieving the calibration result upon application of power to the other chip logic.

Abstract: An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burn-in to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation.

Abstract: An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation.