Patents by Inventor James M. Dewey

James M. Dewey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7391221
    Abstract: One exemplary device has a plurality of leads with termination impedances, and a standard impedance. Among the termination impedances are master impedances arranged to be calibrated by comparison with the standard impedance and slave impedances arranged to be calibrated in accordance with an associated master impedance.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: June 24, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jayen J. Desai, James M. Dewey, David Purvis
  • Patent number: 6041417
    Abstract: The present invention provides a method and apparatus for receiving and synchronizing data transmitted to a host interface unit of a graphics memory system on the rising and falling edges of a strobe signal in accordance with an accelerated graphics port (AGP) specification. An inner loop synchronization component, which is comprised in the host interface unit of the graphics memory system, receives data transmitted to the host interface unit on the falling and rising edges of a strobe signal and synchronizes the data to a PCI clock signal. The inner loop synchronization component comprises a first data transfer unit, a second data transfer unit and a control unit. The first data transfer unit comprises logic configured to capture the data transmitted on the falling edge of the strobe signal and to delay the captured data a predetermined number of cycles of the PCI clock before outputting the captured data from the first data transfer unit.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: March 21, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Maynard D. Hammond, James M. Dewey
  • Patent number: 5862066
    Abstract: Apparatus for performing floating point divide operations includes a divider and a comparator. The divider performs a floating point divide operation on a floating point numerator and a floating point denominator. The comparator performs a comparison of the floating point denominator, except for a sign bit of the floating point denominator, with a floating point value of 0.0. A logic element, responsive to a control signal indicative of the floating point divide operation, provides to the comparator equal sign bits associated with the floating point denominator and the floating point value of 0.0. A result of the comparison indicates a divide by zero operation and is independent of the sign of the floating point denominator. The result of the comparison is used to determine a course of action before the divide operation is completed.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: January 19, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Theodore G. Rossin, Jon L Ashburn, James M Dewey