Patents by Inventor James M. E. Harper

James M. E. Harper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7271486
    Abstract: A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: September 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Roy A. Carruthers, Christophe Detavernier, James M. E. Harper, Christian Lavoie
  • Patent number: 6905560
    Abstract: A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Roy A. Carruthers, Christophe Detavernier, James M. E. Harper, Christian Lavoie
  • Publication number: 20040123922
    Abstract: A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventors: Cyril Cabral, Roy A. Carruthers, Christophe Detavernier, James M. E. Harper, Christian Lavoie
  • Publication number: 20040038489
    Abstract: A method and structure for an integrated circuit transistor structure includes a gate conductor that has a first conductive material and a second material. The invention has non-deformable spacers adjacent the gate conductor and a gap between the gate conductor and the spacer. The first conductive material can be polysilicon and the second material can be either a metal or a polymer. The second material acts as a placeholder for the gap. In the invention, the gap holds ambient gas and decreases resistance of the gate conductor.
    Type: Application
    Filed: August 21, 2002
    Publication date: February 26, 2004
    Inventors: Lawrence A. Clevenger, George C. Feng, James M.E. Harper, Louis L. Hsu
  • Publication number: 20020115262
    Abstract: The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi, and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
    Type: Application
    Filed: February 21, 2001
    Publication date: August 22, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cyril Cabral, Roy Arthur Carruthers, Kevin K. Chan, Guy M. Cohen, Kathryn Wilder Guarini, James M.E. Harper, Christian Lavoie, Paul M. Solomon
  • Patent number: 6300236
    Abstract: A multilayer interconnected electronic component having increased electromigration lifetime is provided. The interconnections are in the form of studs and comprise vertical side walls having a refractory metal diffusion barrier liner along the sidewalls. The stud does not have a barrier layer at the base thereof and the base of the stud contacts the metallization on the dielectric layer of the component. An adhesion layer can be provided between the base of the stud and the surface of the metallization and the adhesion layer may be continuous or discontinuous. The adhesion layer is preferably a metal such as aluminum which dissolves in the stud or metallization upon heating of the component during fabrication or otherwise during use of the component. A preferred component utilizes a dual Damascene structure.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: October 9, 2001
    Assignee: International Business Machines Corporation
    Inventors: James M. E. Harper, Robert M. Geffken
  • Patent number: 6150723
    Abstract: A multilayer interconnected electronic component having increased electromigration lifetime is provided. The interconnections are in the form of studs and comprise vertical side walls having a refractory metal diffusion barrier liner along the sidewalls. The stud does not have a barrier layer at the base thereof and the base of the stud contacts the metallization on the dielectric layer of the component. An adhesion layer can be provided between the base of the stud and the surface of the metallization and the adhesion layer may be continuous or discontinuous. The adhesion layer is preferably a metal such as aluminum which dissolves in the stud or metallization upon heating of the component during fabrication or otherwise during use of the component. A preferred component utilizes a dual Damascene structure.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: November 21, 2000
    Assignee: International Business Machines Corporation
    Inventors: James M. E. Harper, Robert M. Geffken
  • Patent number: 5634973
    Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kevin K. Chan, Jack O. Chu, James M. E. Harper
  • Patent number: 5595600
    Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: January 21, 1997
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kevin K. Chan, Jack O. Chu, James M. E. Harper
  • Patent number: 5565031
    Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: October 15, 1996
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kevin K. Chan, Jack O. Chu, James M. E. Harper
  • Patent number: 5565236
    Abstract: A method for forming a giant magnetoresistance sensor and method for making is described incorporating an oriented granular layer wherein the layer has a copper matrix with magnetic particles of a nickel cobalt alloy wherein the magnetic particles have a magnetocrystalline anisotropy constant K.sub.1 in the range from 0 to 3.times.10.sup.4 ergs/cm.sup.3. Alternatively, a silver or gold matrix may be used with magnetic particles of a nickel-iron alloy. The granular layer preferably has a (100) texture to provide the magnetic particles with their easy axes in the plane of the layer. The magnetic particles have their largest dimension in the range from 40 to 400 angstroms. The invention overcomes the problem of requiring a large magnetic field to obtain the saturation .DELTA.R/R. By providing a granular film with magnetic particles of low anisotropy, the saturation field to obtain .DELTA.R/R may be as low as 10 to 20 Oe.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: October 15, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard J. Gambino, James M. E. Harper, Thomas R. McGuire, Thomas S. Plaskett
  • Patent number: 5510295
    Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10.sup.17 atoms/cm.sup.3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700.degree. C., and more preferably between about 600.degree.-700.degree. C.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: April 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Lawrence A. Clevenger, Francois M. d'Heurle, James M. E. Harper, Randy W. Mann, Glen L. Miles, Donald W. D. Rakowski
  • Patent number: 5427630
    Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.
    Type: Grant
    Filed: May 9, 1994
    Date of Patent: June 27, 1995
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kevin K. Chan, Jack O. Chu, James M. E. Harper
  • Patent number: 5422621
    Abstract: A giant magnetoresistance sensor incorporating an orientated granular layer wherein the layer has a copper matrix with magnetic particles of a nickel cobalt alloy wherein the magnetic particles have a magnetocrystalline anisotropy constant K.sub.1 in the range from 0 to 3.times.10.sup.4 ergs/cm.sup.3. Alternatively, a silver or gold matrix may be used with magnetic particles of a nickel-ion alloy. The granular layer preferably has a (100) texture to provide the magnetic particles with their easy axes in the plane of the layer. The magnetic particles have their largest dimension in the range from 40 to 400 angstroms. The invention overcomes the problem of requiring a large magnetic field to obtain the saturation .DELTA.R/R. By providing a granular film with magnetic particles of low anisotropy, the saturation field to obtain .DELTA.R/R may be as low as 10 to 20 Oe.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: June 6, 1995
    Assignee: International Business Machines Corporation
    Inventors: Richard J. Gambino, James M. E. Harper, Thomas R. McGuire, Thomas S. Plaskett
  • Patent number: 5418188
    Abstract: A method for controlled positioning of a compound layer such as TiSi.sub.2 or CoSi.sub.2 in a multilayer device such as a semiconductor is disclosed. The compound surface layer is situated adjacent to an intermediate layer comprised of one of the two types of atoms present in the molecules of the adjacent compound surface layer. The intermediate layer is also situated adjacent to a base layer, such as a semiconductor substrate. An epitaxial silicon layer is the suggested intermediate layer where the surface layer is comprised of TiSi.sub.2 or CoSi.sub.2. By simultaneously heating the multilayer device and using an appropriate etching process for selectively removing the atoms from the surface of the compound surface layer which are common in both the compound and intermediate layer (i.e., silicon) the intermediate layer can be reduced in thickness and/or fully consumed while the structural integrity of the compound surface layer remains essentially unchanged.
    Type: Grant
    Filed: September 5, 1991
    Date of Patent: May 23, 1995
    Assignee: International Business Machines Corporation
    Inventors: James M. E. Harper, Dan Moy, Shahrnaz Motakef
  • Patent number: 5243222
    Abstract: A method for providing vias, lines and other recesses in VLSI interconnection structures with copper alloys to create a thin layer of an oxide of an alloying element on the surface of the deposited alloy and on portions of the alloy which are in contact with an oxygen containing dielectric is disclosed. The present invention is also directed to VLSI interconnection structures which utilize this copper alloy and thin oxide layer in their vias, lines and other recesses. The oxide layer eliminates the need for diffusion barrier and/or adhesion layers and provides corrosion resistance for the deposited copper alloy. VLSI devices utilizing this copper alloy in the vias, lines and other recesses interconnecting semiconductor regions, devices and conductive layers on the VLSI device are significantly improved.
    Type: Grant
    Filed: January 8, 1992
    Date of Patent: September 7, 1993
    Assignee: International Business Machines Corporation
    Inventors: James M. E. Harper, Karen L. Holloway, Thomas Y. Kwok
  • Patent number: 5143867
    Abstract: A method for filling VLSI high aspect ratio vias and lines in VLSI interconnection structures, with a low resistivity metal at temperatures below 400.degree. C. A low melting point alloy of a desired low resistivity metal is deposited into the high aspect ratio vias or lines. The alloy is then purified in place by bringing the alloying element to the surface of the deposited alloy and removing the element from said surface thereby leaving the low resistivity metal in the interconnection structure. In one embodiment, the alloy is purified by using a low temperature oxidation process to allow the alloying element to diffuse to the surface of the deposited alloy where a surface oxide is formed. The surface oxide is then removed by chemical etching or by chemical mechanical polishing. In a second embodiment, a continuous exposure to a plasma etching or reactive ion etching will steadily remove the alloying element from the surface of the deposited alloy.
    Type: Grant
    Filed: February 13, 1991
    Date of Patent: September 1, 1992
    Assignee: International Business Machines Corporation
    Inventors: Francois M. d'Heurle, James M. E. Harper
  • Patent number: 5130274
    Abstract: A method for providing vias, lines and other recesses in VLSI interconnection structures with copper alloys to create a thin layer of an oxide of an alloying element on the surface of the deposited alloy and on portions of the alloy which are in contact with an oxygen containing dielectric is disclosed. The present invention is also directed to VLSI interconnection structures which utilize this copper alloy and thin oxide layer in their vias, lines and other recesses. The oxide layer eliminates the need for diffusion barrier and/or adhesion layers and provides corrosion resistance for the deposited copper alloy. VLSI devices utilizing this copper alloy in the vias, lines and other recesses interconnecting semiconductor regions, devices and conductive layers on the VLSI device are significantly improved.
    Type: Grant
    Filed: April 5, 1991
    Date of Patent: July 14, 1992
    Assignee: International Business Machines Corporation
    Inventors: James M. E. Harper, Karen L. Holloway, Thomas Y. Kwok
  • Patent number: 4538067
    Abstract: A technique for providing an ion beam of variable focussing (concentration) is described using a flexible grid for extracting and accelerating ions from an ion plasma. The grid is electrically conducting and will bow depending on a voltage difference between it and the ion plasma. This bowing of the grid from its initial planar configuration provides focussing of the ion beam. The amount of focussing depends upon the amount the grid is bowed, which in turn depends upon the voltage difference between it and the ion plasma. The same ion source/flexible grid combination can be used for different operations as for example, providing a collimated, low energy ion beam over a large area and then for providing a focussed ion beam of high energy onto a small area.
    Type: Grant
    Filed: December 9, 1982
    Date of Patent: August 27, 1985
    Assignee: International Business Machines Corporation
    Inventors: Jerome J. Cuomo, James M. E. Harper, Gary A. Waters
  • Patent number: 4523971
    Abstract: This ion beam system provides an ion beam pattern which is produced without the need for a mask. A programmable grid is used in combination with an ion beam source, where the apertures of the programmable grid can have electrical potentials associated therewith which either extract ions or impede the movement of ions through the apertures. Depending upon the electrical biasing provided to each of the apertures of the grid, different patterns of ions can be extracted through the grid. By changing the electrical bias at different locations on the programmable grid, these different patterns are produced. The patterns can be used for many applications, including patterned deposition, patterned etching, and patterned treatment of surfaces.
    Type: Grant
    Filed: June 28, 1984
    Date of Patent: June 18, 1985
    Assignee: International Business Machines Corporation
    Inventors: Jerome J. Cuomo, James M. E. Harper, Harold R. Kaufman, James L. Speidell