Abstract: The present invention provides apparatus and methods for billing a packet switched call utilizing a prepaid account in which a prepaid packet note (PPN) monitors a subscriber's usage during the call. The PPN is logically associated with a wireless packet serving node (WPSN) that executes call processing that is associated with the call. Moreover, the present invention provides apparatus and method for enabling the subscriber to replenish the subscriber's prepaid account.

Abstract: The present invention enables a wireless communications system to support prepaid charging for a packet-switched call and a circuit-switched call that are associated with a subscriber and that are coexistent. The present invention utilizes an integrated accounting processor that fetches an amount remaining in the subscriber's prepaid account and determines a balance that the subscriber may consume. An integrated prepaid node (IPPN) that is logically associated with an integrated wireless packet services node (IWPSN) monitors the usage associated with the packet-switched call and the circuit-switched call. When the packet-switched call ends, the IPPN reports the usage consumed during the packet-switched call and the circuit-switched call to the integrated accounting processor. The integrated accounting processor adjusts the subscriber's prepaid account in accordance with the usage.

Abstract: A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus.

Abstract: A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus.

Abstract: Disclosed is a computer system (FIG. 1) that is operable with any multiplexed-address memory (200) within a size range of 2.sup.N to 2.sup.N+R memory locations (211). The system has a memory of 2.sup.S locations selected from the predetermined range, and the memory has S/2 multiplexed address input terminals (231). Address bits forming a memory address, generated for example by a processor (400), are multiplexed by a memory controller (300) onto N/2+R address output terminals (314) in two sets of N/2+R address bits. The address bit sets have at least R/2 bits in common. An address bus (250) transports the multiplexed address bits to the memory. The bus has N/2+R address leads (251) connected to the output terminals of the memory controller. S/2 of those address leads are also connected to the address input terminal of the memory. The remaining address leads are not connected. The memory controller multiplexes the address of any memory within the predetermined range onto its output terminals.

Abstract: In a processor system having a central processor and secondary support processor mounted on a backplane board, a separate peripheral interrupt bus is provided for each secondary support processor to give full interrupt priority capability to peripheral devices connected to the support processors. The support processors (110, 120) and certain of the system's peripheral interface circuits (102, 104) are connected to the system's central processor (101) via a primary interrupt bus (105) and other peripheral interface circuits (112, 114, 122) are connected to their associated secondary processors (110, 120) via separate interrupt buses (115, 125) all on the same backplane board. The backplane board is divided into an upper section and a lower section and the primary interrupt bus and the interrupt request and acknowledge terminal pins for all circuit boards are in the lower section.

Abstract: A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space; a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus.

Abstract: In a communication system which includes a plurality of stations interconnected for communications by a first bus, a second station includes a device, such as a processor, and a resource, such as a memory or a peripheral unit, interconnected for communication by a second bus. An interface mechanism connecting the first bus with the second bus allows the device to access the first bus over the second bus, and allows a first station to access the resource via the first and second buses. Deadlock detection circuitry detects cotemporaneous attempts by the device to access the first bus and attempts by the first station to access the resource. Deadlock resolution circuitry responds to deadlock detection by disconnecting the device from the second bus to allow the first station to access the resource, and by reconnecting the device to the second bus when the first station ceases to access the resource.