Abstract: A semiconductor device characterized by a field limiting ring formed by a number of field limiting cells that define wells which are laterally diffused to form a continuous equipotential ring between interior and exterior regions of a semiconductor device. A number of active cells are formed in the interior region, and are therefore delineated from the exterior region of the device. Each of these active cells is a transistor, and preferably a field-effect transistor, whose structure is essentially identical to the field limiting cells, except that their wells are not merged but instead are isolated from each other. The field limiting ring increases the breakdown voltage and the ruggedness of device, and therefore enables the device to sustain high voltages when the device is in the off-state. The process does not require masking, implanting and diffusion steps for the sole purpose of forming the field limiting ring, but is instead fully integrated with the semiconductor process for forming the active cells.

Abstract: A trench capacitor within an integrated circuit is provided which is filled with solid elemental metal. This metal-filled trench capacitor is formed by the following steps. First a trench is conventionally formed within a silicon substrate. A dielectric film is then blanket deposited onto the substrate and within the trench, so that the walls and bottom surface of the trench are completely covered. A metal-containing liquid solution is next deposited within the trench, and heated to a temperature sufficient to thermally decompose the metal compound within the liquid solution and drive off any solvent from the solution, thereby leaving a plate of elemental metal within the trench capacitor. The metal-filled capacitor is accordingly characterized by high electrical conductivity. The method may also be utilized to form a metal contact to a buried layer within an integrated circuit; a rectifying contact or Schottky diode; contacts to the substrate; metal diffusion barrier layer; and interconnection metallization.

Abstract: A process for forming a vertical n-channel DMOS transistor uses a common deposition step to form a phosphorus-rich predeposit simultaneously over the polysilicon gate electrode, over a central surface portion of a p-well region and over the back surface drain region of the chip. This predeposit is followed by a common drive-in step to form an n-type source region within the p-well region, and to make the polysilicon gate electrode and the back surface more conductive. In addition, the process uses the source region contact mask as a shadow mask for anistropically etching a via hole in the source region so that the source metallization can also contact the p-well region and serve also as a shorting contact to the p-well.