Abstract: An input circuit for a wide acquisition range minimum shift keying demodulator includes a pair of phase-locked loops (PLL). Each PLL is designed to receive from a frequency doubler a respective one of two discrete spectral lines in the frequency spectrum separated by a frequency equal to the bit rate. Each PLL operates at one of three frequencies including its own search position frequency and the search position frequency of the other PLL plus or minus the bit rate. A logic decision circuit responsive to the PLLs operates with a frequency synthesizer connected to a mixer at the input of the doubler so that when one PLL locks to one spectral line, the other PLL is operated at its respective frequencies to lock to the other spectral line.