Patents by Inventor James M. Larnerd
James M. Larnerd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7814649Abstract: A method of making a circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer.Type: GrantFiled: July 10, 2006Date of Patent: October 19, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
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Patent number: 7491896Abstract: An information handling system, e.g., a mainframe computer, which includes as part thereof a housing having therein an electrical assembly including a circuitized substrate which in turn includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within the system. At least one electrical component is positioned on and electrically coupled to the circuitized substrate of the system's electrical assembly.Type: GrantFiled: January 18, 2008Date of Patent: February 17, 2009Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
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Patent number: 7377033Abstract: A method of making circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. An information handling system, e.g., a mainframe computer, which represents one of the products in which the substrate may be utilized, is also provided.Type: GrantFiled: December 20, 2006Date of Patent: May 27, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
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Patent number: 7348677Abstract: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.Type: GrantFiled: April 5, 2006Date of Patent: March 25, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: James M. Larnerd, John M. Lauffer, Voya R. Markovich, Kostas I. Papathomas
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Patent number: 7211289Abstract: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.Type: GrantFiled: December 18, 2003Date of Patent: May 1, 2007Assignee: Endicott Interconnect Technologies, Inc.Inventors: James M. Larnerd, John M. Lauffer, Voya R. Markovich, Kostas I. Papathomas
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Patent number: 7157646Abstract: A circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.Type: GrantFiled: July 2, 2004Date of Patent: January 2, 2007Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
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Patent number: 7157647Abstract: A circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.Type: GrantFiled: July 2, 2004Date of Patent: January 2, 2007Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
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Patent number: 6483046Abstract: The present invention provides a circuit board having burr free castellated plated through holes. In particular, the leading edge of the plated through hole, that tends to produce burr formation during conventional profiling, is removed or pre-profiled to off-set the leading edge of the plated through hole from a surface of the circuit board.Type: GrantFiled: April 24, 2000Date of Patent: November 19, 2002Assignee: International Business Machines CorporationInventors: David E. Houser, James M. Larnerd, Jeffrey L. Lee, Francis S. Poch
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Patent number: 6105246Abstract: The present invention provides a method of creating a circuit board having burr free castellated plated through holes. In particular, the leading edge of the plated through hole, that tends to produce burr formation using conventional profiling methods, is removed or pre-profiled. The pre-profiled plated through hole is then profiled at a distance slightly off-set from the pre-profiled edge to further prevent burr formation.Type: GrantFiled: May 20, 1999Date of Patent: August 22, 2000Assignee: International Business Machines CorporationInventors: David E. Houser, James M. Larnerd, Jeffrey L. Lee, Francis S. Poch
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Patent number: 4979862Abstract: An automatic loading mechanism for use in the manufacture of thin, metallic circuit board panels. The invention includes a lower drum unit which accepts the metallic panels from a conveyor system. The lower drum unit is rotatably mounted within a frame assembly, and includes a plurality of clamps which can automatically receive several metallic panels of varying size. The lower unit includes automatic clamp control means, and has the capability of rotating the panels from a horizontal to a vertical position or vice-versa. The lower drum unit guidingly feeds the metallic panels, through a spline assembly, to an upper unit. The uppper unit includes a plurality of clamps, in diametrically placed pairs, which delicately handle only the peripheral edge of the metallic panels while feeding them automatically into a rack assembly.Type: GrantFiled: December 23, 1988Date of Patent: December 25, 1990Assignee: IBMInventors: Richard A. Bartlett, Dominic A. Casale, John J. Konrad, James M. Larnerd, Donald R. Olson, Charles R. Pigos, Jr.
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Patent number: 4869418Abstract: A method and apparatus for producing flush solder fill over recessed pins and over passage holes in circuitized substrates. A substrate carrying rack is immersed in a vessel of molten solder after it has been similarly immersed in a flux bath. While in the molten solder, the rack is vigorously agitated. The rack is then withdrawn from the molten solder and is pivoted upwardly while positioned over the molten solder. Simultaneously, an anvil is rotated from a home position to an impact position at precisely the correct moment. With the solder still molten on the substrate surfaces, the rack is then permitted to descend and is positively biased to strike the anvil thereby dislodging any excess molten solder. A unique supporting arrangement for the rack insures that only a minimum of mass acutally impacts against the anvil while insuring the effectiveness of the operation.Type: GrantFiled: November 9, 1988Date of Patent: September 26, 1989Assignee: International Business Machines CorporationInventors: John P. Simpson, Gary L. Newman, James M. Larnerd, Alan J. Emerick
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Patent number: 4799616Abstract: A method and apparatus for producing flush solder fill over recessed pins and over passage holes in circuitized substrates. A substrate carrying rack is immersed in a vessel of molten solder after it has been similarly immersed in a flux bath. While in the molten solder, the rack is vigorously agitated. The rack is then withdrawn from the molten solder and is pivoted upwardly while positioned over the molten solder. Simultaneously, an anvil is rotated from a home position to an impact position at precisely the correct moment. With the solder still molten on the substrate surfaces, the rack is then permitted to descend and is positively biased to strike the anvil thereby dislodging any excess molten solder. A unique supporting arrangement for the rack insures that only a minimum of mass actually impacts against the anvil while insuring the effectiveness of the operation.Type: GrantFiled: October 6, 1987Date of Patent: January 24, 1989Assignee: International Business Machines CorporationInventors: John P. Simpson, Gary L. Newman, James M. Larnerd, Alan J. Emerick