Abstract: A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.

Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

Abstract: A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material.

Abstract: A synchronized optical clocking signal is provided to a plurality of optical receivers by providing a layer of a high absorption coefficient material, such as SiGe or Ge, on a front surface of a low absorption coefficient substrate, such as silicon. Diodes are formed in the germanium containing layer for receiving an optical signal and converting the optical signal into an electrical signal. An optical clocking signal is shined on the back surface of the silicon substrate. The light has a wavelength long enough so that it penetrates through the silicon substrate to the germanium containing layer. The wavelength is short enough so that the light is absorbed in the germanium containing layer and converted to the electrical clocking signal used for neighboring devices and circuits. The germanium concentration is graded so that minority carriers are quickly swept across junctions of the diodes and collected.

Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

Abstract: A diaphragm (12) for use with a fluid carrying condiuit (70) or outer body (14) where the diaphragm (12) has a convex outer surface (26), a concave inner surface (28), a slit (32) extending from surface (26) to surface (28), and a notch defined by two walls (40, 42) at outer surface (26). The walls (40, 42) preferably diverge towards the outlet end (20) so that upon deflection of diaphragm (12), a greater minimum gap (46) for fluid movement is created when compared to the minimum gap (48) of a diaphragm not having the notch. The notch may have a cross section shape of a “V”, a “U”, or a three section rectilinear form, and may be formed at either surface depending upon the direction of diaphragm deflection.

Abstract: A synchronized optical clocking signal is provided to a plurality of optical receivers by providing a layer of a high absorption coefficient material, such as SiGe or Ge, on a front surface of a low absorption coefficient substrate, such as silicon. Diodes are formed in the germanium containing layer for receiving an optical signal and converting the optical signal into an electrical signal. An optical clocking signal is shined on the back surface of the silicon substrate. The light has a wavelength long enough so that it penetrates through the silicon substrate to the germanium containing layer. The wavelength is short enough so that the light is absorbed in the germanium containing layer and converted to the electrical clocking signal used for neighboring devices and circuits. The germanium concentration is graded so that minority carriers are quickly swept across junctions of the diodes and collected.

Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

Abstract: A diaphragm (12) for use with a fluid carrying conduit (70) or outer body (14) where the diaphragm (12) has a convex outer surface (26), a concave inner surface (28), a slit (32) extending from surface (26) to surface (28), and a notch defined by two walls (40, 42) at outer surface (26). The walls (40, 42) preferably diverge towards the outlet end (20) so that upon deflection of diaphragm (12), a greater minimum gap (46) for fluid movement is created when compared to the minimum gap (48) of a diaphragm not having the notch. The notch may have a cross section shape of a “V”, a “U”, or a three section rectilinear form, and may be formed at either surface depending upon the direction of diaphragm deflection.

Abstract: A memory cell is constructed with one electrode of the transfer device extending over a trench capacitor, saving about 6.5% of cell area. Selective polysilicon for a strap seeded from the trench is grown in the same step in which selective single crystal silicon seeded from the substrate is grown for the transfer device. At least a portion of the node diffusion is located in single crystal epitaxial silicon extending over the trench. The process eliminates the need for a separate strap masking step.

Abstract: A memory cell is constructed with one electrode of the transfer device extending over a trench capacitor, saving about 6.5% of cell area. Selective polysilicon for a strap seeded from the trench is grown in the same step in which selective single crystal silicon seeded from the substrate is grown for the transfer device. At least a portion of the node diffusion is located in single crystal epitaxial silicon extending over the trench. The process eliminates the need for a separate strap masking step.

Abstract: A megasonic liquid stream semiconductor wafer cleaning apparatus and method uniformly removes debris from all points on the surface of a semiconductor wafer. The wafer is rotated about a proscribed axis while the means for producing focused megasonic waves and a liquid stream of cleaning fluid is focused on the wafer so as to apply sufficient energy to clean the wafer yet not cause damage to the electronic circuity embedded in the wafer. A method is provided for moving the outlet port providing the stream of megasonic cleaning fluid across the wafer so that the amount of energy applied to any area of the wafer is relatively constant.

Abstract: A method of forming a sub-lithographic image formed by the intersection of two spacers. A substrate with a first pattern of selectively etchable material with sidewalls that are substantially vertical is provided. A first sidewall spacer is formed of a material that is selectively etchable relative to the first pattern material. A second pattern of a selectively etchable material is formed with the second pattern intersecting the first pattern. The sidewalls of the second pattern are substantially vertical as well. A second sidewall spacer is formed of a material that is selectively etchable relative to the second pattern material. The second pattern material is etched to leave the second sidewall spacer.

Abstract: A method of forming a sub-lithographic image formed by the intersection of two spacers. A substrate with a first pattern of selectively etchable material with sidewalls that are substantially vertical is provided. A first sidewall spacer is formed of a material that is selectively etchable relative to the first pattern material. A second pattern of a selectively etchable material is formed with the second pattern intersecting the first pattern. The sidewalls of the second pattern are substantially vertical as well. A second sidewall spacer is formed of a material that is selectively etchable relative to the second pattern material. The second pattern material is etched to leave the second sidewall spacer. Alternatively, the first and/or second pattern materials may be totally removed, left in place, or planarized.

Abstract: A method of forming a sub-lithographic image formed by the intersection of two spacers. A substrate with a first pattern of selectively etchable material with sidewalls that are substantially vertical is provided. A first sidewall spacer is formed of a material that is selectively etchable relative to the first pattern material. A second pattern of a selectively etchable material is formed with the second pattern intersecting the first pattern. The sidewalls of the second pattern are substantially vertical as well. A second sidewall spacer is formed of a material that is selectively etchable relative to the second pattern material. The second pattern material is etched to leave the second sidewall spacer. Alternatively, the first and/or second pattern materials may be totally removed, left in place, or planarized.

Abstract: An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Abstract: An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.