Abstract: A challenge/response system separates a physically unclonable function from the challenge/response. Bits in a challenge are used to qualify random data values. The random data values are permuted to generate a result. The result is used to encrypt a response that is sent in reply to the challenge. Additional permuting mechanisms may be used to further obfuscate the response.

Abstract: A challenge/response system separates a physically unclonable function from the challenge/response. Bits in a challenge are used to qualify random data values. The random data values are permuted to generate a result. The result is used to encrypt a response that is sent in reply to the challenge. Additional permuting mechanisms may be used to further obfuscate the response.

Abstract: System and method for performing correlation analysis. A program that includes multiple program structures and one or more data objects is stored. Each data object is shared by at least two of the program structures. For each program structure, decomposition effects on each of the data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied to the program structure are analyzed. One or more groups of correlated structures are determined based on the analyzing. Each group includes two or more program structures that share at least one data object, and at least one optimizing transform that is compatible with respect to the two or more program structures and the shared data object. For at least one group, the at least one optimizing transform is usable to transform the two or more program structures to meet a specified optimization objective.

Abstract: System and method for performing correlation analysis. A program that includes multiple program structures and one or more data objects is stored. Each data object is shared by at least two of the program structures. For each program structure, decomposition effects on each of the data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied to the program structure are analyzed. One or more groups of correlated structures are determined based on the analyzing. Each group includes two or more program structures that share at least one data object, and at least one optimizing transform that is compatible with respect to the two or more program structures and the shared data object. For at least one group, the at least one optimizing transform is usable to transform the two or more program structures to meet a specified optimization objective.

Abstract: System and method for performing correlation analysis. A program that includes multiple program structures and one or more data objects is stored. Each data object is shared by at least two of the program structures. For each program structure, decomposition effects on each of the data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied to the program structure are analyzed. One or more groups of correlated structures are determined based on the analyzing. Each group includes two or more program structures that share at least one data object, and at least one optimizing transform that is compatible with respect to the two or more program structures and the shared data object. For at least one group, the at least one optimizing transform is usable to transform the two or more program structures to meet a specified optimization objective.

Abstract: System and method for performing correlation analysis. A program that includes multiple program structures and one or more data objects is stored. Each data object is shared by at least two of the program structures. For each program structure, decomposition effects on each of the data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied to the program structure are analyzed. One or more groups of correlated structures are determined based on the analyzing. Each group includes two or more program structures that share at least one data object, and at least one optimizing transform that is compatible with respect to the two or more program structures and the shared data object. For at least one group, the at least one optimizing transform is usable to transform the two or more program structures to meet a specified optimization objective.

Abstract: An electronic asymmetric unclonable function applied to an electronic system being evaluated includes an electronic system and an AUF array electronically associated with the electronic system. The AUF array includes a plurality of non-identical cells. Each of the non-identical cells includes a test element representing a characteristic of the electronic system being evaluated and a measurement device evaluating the test element. A comparison unit processes an output of the measurement device to provide a multi-bit output value representing a magnitude of differences.

Abstract: An electronic asymmetric unclonable function applied to an electronic system being evaluated includes an electronic system and an AUF array electronically associated with the electronic system. The AUF array includes a plurality of non-identical cells. Each of the non-identical cells includes a test element representing a characteristic of the electronic system being evaluated and a measurement device evaluating the test element. A comparison unit processes an output of the measurement device to provide a multi-bit output value representing a magnitude of differences.

Abstract: A self-modifying FPGA system includes an FPGA and a configuration memory coupled to the FPGA for providing the FPGA with configuration data including SAFE configuration data and dormant configuration data. The SAFE configuration data is initially loaded to the FPGA and the FPGA is configured to a safe operating mode. Upon a determination to proceed to a next step of self modification, dormant configuration data contained in the configuration memory is loaded into the FPGA and the FPGA is configured to a secure operating mode.

Abstract: A system employs physical unclonable functions of an integrated circuit for detecting integrated circuits and protecting products and technology from integrated circuits which have been subject to tampering, stressing and replacement, and counterfeit components. The system includes a sensor detecting a characteristic impedance generated as a result of controlled access to a memory device of the integrated circuit. The characteristic impedance is applied in the creation of a discrimination matrix of values based on electrical interface signals for the integrated circuit. The sensor includes a ring oscillator and associated monitoring components. The ring oscillator is composed of the memory device of the integrated circuit and a sensory circuitry, wherein changes in a frequency generated by the ring oscillator is indicative of changes in circuitry.

Abstract: An electronic asymmetric unclonable function applied to an electronic system being evaluated includes an electronic system and an AUF array electronically associated with the electronic system. The AUF array includes a plurality of non-identical cells. Each of the non-identical cells includes a test element representing a characteristic of the electronic system being evaluated and a measurement device evaluating the test element. A comparison unit processes an output of the measurement device to provide a multi-bit output value representing a magnitude of differences.

Abstract: An electronic asymmetric unclonable function applied to an electronic system being evaluated includes an electronic system and an AUF array electronically associated with the electronic system. The AUF array includes a plurality of non-identical cells. Each of the non-identical cells includes a test element representing a characteristic of the electronic system being evaluated and a measurement device evaluating the test element. A comparison unit processes an output of the measurement device to provide a multi-bit output value representing a magnitude of differences.

Abstract: A method for combating counterfeiting and tampering of integrated circuits includes the steps providing a programmable logic device, the programmable logic device including an arithmetic circuit implemented into the substrate, and constructing an arithmetic feedback oscillator using the arithmetic circuit. The step of constructing the arithmetic feedback oscillator includes incorporating a feedback loop into the arithmetic circuit and feeding output bits back into an input of the arithmetic circuit. The method also includes the step of selecting input values producing repeating values in a lesser order bit of a product of the arithmetic circuit when first and second input are applied to the arithmetic circuit and monitoring the lesser order bit and determining a predicted pattern.

Abstract: System and method for approximating a system. A multi-parameter representation of a family of systems is stored. An embedding of the family into an abstract geometrical continuous space with a metric and defined by the parameters is determined. Coordinates of the space specify values for the parameters of systems of the family. The space includes a grid of points representing respective discrete approximations of the systems. A first point corresponding to a desired instance of a system is determined. The first point's coordinates specify values for the parameters of the instance. The space is sampled using a mapping of a well-distributed point set from a Euclidean space of the parameters to the abstract space. A nearest discrete point to the first point is determined which specifies values for parameters for an optimal discrete approximation of the desired instance, which are useable to implement the discrete approximation of the desired instance.

Abstract: A method for combating counterfeiting and tampering of integrated circuits includes the steps providing a programmable logic device, the programmable logic device including an arithmetic circuit implemented into the substrate, and constructing an arithmetic feedback oscillator using the arithmetic circuit. The step of constructing the arithmetic feedback oscillator includes incorporating a feedback loop into the arithmetic circuit and feeding output bits back into an input of the arithmetic circuit. The method also includes the step of selecting input values producing repeating values in a lesser order bit of a product of the arithmetic circuit when first and second input are applied to the arithmetic circuit and monitoring the lesser order bit and determining a predicted pattern.

Abstract: A sensor system for protecting products and technology from reverse engineering by detecting attempts to probe electronic circuitry includes a sensor electrically linked to electronic circuitry. The sensor detects interaction of probe devices with the electronic circuitry for the purpose of reverse engineering the electronic circuitry. The sensor includes an exciter and an impedance counter linked to the exciter. A count rate of the impedance counter is a function of the impedance of the electronic circuitry due to the fact that oscillation frequency generated by the exciter is also a function of the impedance of the electronic circuitry. The sensor also includes an impedance register storing the binary count value from the impedance counter, wherein after the impedance counter data is transferred into the impedance register, the data is referred to as impedance data.

Abstract: A self-modifying FPGA system includes an FPGA and a configuration memory device coupled to the FPGA for providing the FPGA with configuration information. The configuration memory device is programmed with configuration data and dormant data. The FPGA system is also provided with a configuration assist circuit coupled to the FPGA and the configuration memory device for controlling loading of configuration information from the configuration memory device to the FPGA. A tamper detection system provides a tamper signal to the FPGA, wherein when a tamper signal is received by the FPGA the configuration data is replaced with the dormant data.

Abstract: System and method for implementing multi-channel operations in a programmable hardware element (PHE). A hardware configuration program, including a processing function, inputs and outputs of the processing function, a plurality of channels, and channel scanning functionality for the plurality of channels, is specified. A PHE is configured with the hardware configuration program, including implementing the processing function and the channel scanning functionality on the PHE. A respective state and configuration of each of the plurality of channels is stored in a memory of the PHE to enable logic-sharing between each of the plurality of channels. The PHE is operated, including performing channel scanning on the plurality of channels, and updating the configuration of one or more of the channels in the memory of the PHE without interrupting the channel scanning, without taking any of the channels offline, and/or without interrupting a continuity of an output of the PHE.

Abstract: A system and method for creating a graphical program. A function block may be displayed in a graphical program. The graphical program may include a plurality of interconnected blocks which visually indicate the functionality of the program. Additionally, the function block may be operable to perform a first function and may include one or more inputs and one or more outputs. User input specifying an attribute behavior for the function block may be received, e.g., via a menu which allows selection or definition of attribute behaviors, a graphical wizard, or another graphical program, among other methods. The attribute behavior specified for the function block may be usable to determine at attribute of at least a subset of the one or more outputs of the function block based on an attribute of at least one of the one or more inputs to the function block.

Abstract: A system employs physical unclonable functions of an integrated circuit for detecting integrated circuits and protecting products and technology from integrated circuits which have been subject to tampering, stressing and replacement, and counterfeit components. The system includes a sensor detecting a characteristic impedance generated as a result of controlled access to a memory device of the integrated circuit. The characteristic impedance is applied in the creation of a discrimination matrix of values based on electrical interface signals for the integrated circuit. The sensor includes a ring oscillator and associated monitoring components. The ring oscillator is composed of the memory device of the integrated circuit and a sensory circuitry, wherein changes in a frequency generated by the ring oscillator is indicative of changes in circuitry.