Abstract: A method of determining a phase error of an input signal. An input signal is received and sampled. A first value of the input signal is determined at a first instance of time, a second value of the input signal is determined at a second instance of time, and a third value of the input signal is determined at a third instance of time. The third instance of time is between the first and the second instances of time. A phase error of the input signal is determine, based on a comparison of the third value to a threshold value. The timing of the sampling is controlled to minimize the phase error.

Abstract: An adaptive slicer threshold generation system includes a first moving average filter to determine a first average value of a first binary signal. A second moving average filter is included to determine a second average value of a second binary signal. A combiner combines the first average value of the first binary signal and the second average value of the second binary signal to generate a combined output.

Abstract: An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad.

Abstract: A converter includes at least two series coupled integrators, a comparator and a feedback element. The converter provides digital domain scaling so that an output signal is a scaled version of an input signal based on a feedback factor of the feedback element.