Abstract: In the manufacture of an integrated circuit, steps of the process are dynamically augmented, so as to fabricate the integrated circuit at wafer locations which avoid the presence of circuit-killing particulates. During the respective steps of fabrication, the components employed in the process are scanned to locate and identify particulates. This information is compared with a previously defined component/interconnect layout to determine whether the particulates reside at locations that will not detrimentally impact the completed circuit or whether further processing will incorporate the defect into the circuit and render it effectively useless. In this latter circumstance the intended geometries of the circuit are modified, so as to effectively rearrange or shift prescribed components (e.g. semiconductor regions, contact apertures, interconnect tracks) to a location of the wafer which are not coincident with the location of the particulates.

Abstract: A high speed signal processor contains a set of repetitive architecture functional units including an input data storage unit for storing quantized data values, a data shifting unit, an output data accumulator and a control code generator. The data shifting unit is coupled in parallel to each of a plurality of controllable data accumulator sections of the output data accumulator. Each accumulator section has a control input coupled to a respective output of the control data generator for defining the logic operation of the data accumulator section with respect to the contents of the data shifting unit. The data shifting unit has a plurality of stages each of which is coupled in parallel to the output stage of successive stages of the input data storage unit to which successive digitized data samples of a signal waveform to be processed are coupled.

Abstract: An integrated circuit architecture methodology effectively comprises the use of high level building blocks (termed macro-cells) that are composed of a customized arrangement of a number of smaller but readily chip-layout repeatable building blocks termed micro-cells. The size of each macro-cell is determined by signal processing design/performance/operational parameters of the system. The internal configuration geometry and signal port connections of each microcell are customized for circuit packaging density, performance and interconnectability with other micro-cells.