Abstract: A delay correction circuit is described for use with an elastic store in a PCM time division multiplexed system. The relative position of the read and write addresses supplied to the elastic store are monitored. In the event that either the read or write addresses are overtaking the other and are within a predetermined range of addresses, either the read or write address source will be initialized at a predetermined time such that the read and write addresses have new relative position.

Abstract: A carrier terminal unit for interfacing 1.544 MHz PCM lines to a digital switch, wherein voice samples are switched at 2.048 MHz, provides bit synchronization, in-frame monitoring, delay equalization and correction, framing detection, and rate and format conversion. A common memory is utilized for the delay equalization and correction, framing detection and rate and format conversion functions. The memory acts as an elastic store for delay equalization. Delay correction is provided by monitoring the relative positions of the memory read and write addresses and initializing the write addresses after an overtaking of the read or write addresses by the other is detected. Rate and format conversion are provided by storing incoming PCM samples in the memory and reading the samples out in accordance with a predetermined sequence. Framing detection is provided by storing in memory every nth bit of three alternate frames of incoming data.