Abstract: An integrated circuit two-stage power amplifier provides a high-voltage, series-biased FET amplifier for high-efficiency applications. An input is connected to an input matching network, and a driver cell provides power from the input matching network to an interstage power dividing network. Multiple similar cells in a second stage are connected between the interstage power dividing network and an output matching and combining network and are biased by a series-connected active biasing network. An output is connected to the output matching and combining network. One series-connected active biasing network includes series-connected resistances and a second string of series-connected buffer cells connected between the series-connected resistances and the RF power cells for biasing the RF cells.TABLE 1 ______________________________________ State-of-the-Art, Ka-band MMIC Results Freq. Power Gain PAE BW Chip (GHz) (W) (dB) (%) (GHz) #Stg. Voltage ______________________________________ 33 0.66 16.2 41.1 2.

Abstract: A travelling-wave Mach-Zehnder electro-optic modulator (10) for operation at microwave electrical input signal frequencies has an electrical modulation electrode structure (26,34) which constitutes a coplanar waveguide (24). An electrical input signal connector (80) is coupled to a microstrip line (38) having an output impedance which is significantly different from the input impedance of the waveguide (24). A Chebyshev impedance matching transformer (50) couples the input signal from the input connector (80) to the modulation electrode structure (26,34), while matching the output impedance of the microstrip line (38) to the input impedance of the waveguide (24) to maximize the coupling efficiency and minimize return loss. The modulatoGOVERNMENT RIGHTSThis invention was made with Government support under Contract No. N66604-87-C-1126 awarded by the Department of the Navy. The Government has certain rights in this invention.

Abstract: Disclosed herein is an N-way, broad band planar power divider/combiner circuit for dividing or combining RF signals which includes a tapered strip of electrically conductive material having a plurality of conductor fingers which define a plurality of ports at the wide end of the taper, and having a narrow end which defines single port. The tapered metal strip is mounted onto a dielectric slab, and isolation resistors connect adjacent fingers. A single RF signal can be fed into the single port which will be divided into a plurality of signals of equi-amplitude and equi-phase. Conversely, a plurality of RF signals can be fed into the ports at the wide end which will be combined into a single signal.

Abstract: A chip-level power combiner comprises plural amplifier devices, a power divider, and a power combiner. The power divider and the power combiner are disposed in mirror-image fashion. Each divider/combiner comprises a first divider/combiner section having plural branch transmission lines cascading from/to a main transmission line, and a second divider/combiner section having plural feeder transmission lines cascading from/to each branch of the transmission line. Each of the branch and feeder transmission lines has an isolation resistor interposed between adjacent lines, and the feeder transmission lines are tapered.

Abstract: A power amplifier that divides input power among a plurality of parallel channels through a radial line divider, amplifies the power in each channel with three terminal devices, and combines the amplified power in a radial line combiner to produce an output signal. The radial line divider/combiner includes a radial transmission line having a plurality of sectors symmetrically disposed around the inner radius of a supporting annular substrate. The sectors are connected to respective three terminal devices through microstrip transmission lines, and are isolated from laterally adjacent sectors by thin film isolation resistors.