Patents by Inventor James M. Shehadi
James M. Shehadi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10516439Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.Type: GrantFiled: August 1, 2017Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenein, James M. Shehadi
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Publication number: 20190332469Abstract: An in-band error correcting code (ECC) module intercepts input/output (I/O) operations directed to a memory. The in-band ECC module determines whether the I/O is directed to data that needs to be protected against error. In response to determining that the I/O is directed to data that needs to be protected against error, the in-band ECC module directs a memory controller to store or access ECC data corresponding to the data in a first preassigned area of the memory, and to store or access the data in a second preassigned area of the memory.Type: ApplicationFiled: July 5, 2019Publication date: October 31, 2019Inventors: Amir A. RADJAI, Nagi ABOULENEIN, Steve L. GEIGER, Satyajit A. JADHAV, Bezan J. KAPADIA, Vivek KOZHIKKOTTU, Rashmi LAKKUR SUBRAMANYAM, Srithar RAMESH, James M. SHEHADI, Jason D. VAN DYKEN
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Publication number: 20170359099Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.Type: ApplicationFiled: August 1, 2017Publication date: December 14, 2017Applicant: Intel CorporationInventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenein, James M. Shehadi
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Patent number: 9722663Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.Type: GrantFiled: March 28, 2014Date of Patent: August 1, 2017Assignee: Intel CorporationInventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenein, James M. Shehadi
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Publication number: 20150280781Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Applicant: Intel CorporationInventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenien, James M. Shehadi
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Patent number: 9009540Abstract: A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.Type: GrantFiled: December 5, 2012Date of Patent: April 14, 2015Assignee: Intel CorporationInventors: Christopher P. Mozak, Theodore Z. Schoenborn, James M. Shehadi, David G. Ellis, Tomer Levy, Zvika Greenfield
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Patent number: 9009531Abstract: A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.Type: GrantFiled: December 5, 2012Date of Patent: April 14, 2015Assignee: Intel CorporationInventors: Christopher P. Mozak, Theodore Z. Schoenborn, James M. Shehadi, David G. Ellis
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Patent number: 9003246Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.Type: GrantFiled: September 29, 2012Date of Patent: April 7, 2015Assignee: Intel CorporationInventors: Christopher P. Mozak, Theodore Z. Schoenborn, James M. Shehadi
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Patent number: 8996934Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.Type: GrantFiled: September 29, 2012Date of Patent: March 31, 2015Assignee: Intel CorporationInventors: Christopher P. Mozak, Theodore Z. Schoenborn, James M. Shehadi
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Publication number: 20140157055Abstract: A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Inventors: CHRISTOPHER P. MOZAK, Thoedore Z. Schoenborn, James M. Shehadi, David G. Ellis, Tomer Levy, Zvika Greenfield
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Publication number: 20140157053Abstract: A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Inventors: CHRISTOPHER P. MOZAK, Theodore Z. Schoenborn, James M. Shehadi, David G. Ellis
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Publication number: 20140095946Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.Type: ApplicationFiled: September 29, 2012Publication date: April 3, 2014Inventors: Christopher P. Mozak, Theodore Z. Schoenborn, James M. Shehadi
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Publication number: 20140095947Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.Type: ApplicationFiled: September 29, 2012Publication date: April 3, 2014Inventors: Christopher P. Mozak, Theodore Z. Schoenborn, James M. Shehadi