Patents by Inventor James M. Wark
James M. Wark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446440Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: August 21, 2018Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Publication number: 20180358263Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Patent number: 10062608Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: May 2, 2017Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Publication number: 20170283954Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: ApplicationFiled: May 2, 2017Publication date: October 5, 2017Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Patent number: 9640433Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: February 10, 2014Date of Patent: May 2, 2017Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Publication number: 20140154879Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: ApplicationFiled: February 10, 2014Publication date: June 5, 2014Applicant: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Patent number: 8669179Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.Type: GrantFiled: July 11, 2013Date of Patent: March 11, 2014Assignee: Micron Technology, Inc.Inventors: Salman Akram, Charles M. Watkins, William M. Hiatt, David R. Hembree, James M. Wark, Warren M. Farnworth, Mark E. Tuttle, Sidney B. Rigg, Steven D. Oliver, Kyle K. Kirby, Alan G. Wood, Lu Velicky
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Patent number: 8647982Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: March 10, 2009Date of Patent: February 11, 2014Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William M. Hiatt
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Publication number: 20130295766Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.Type: ApplicationFiled: July 11, 2013Publication date: November 7, 2013Inventors: Salman Akram, Charles M. Watkins, William M. Hiatt, David R. Hembree, James M. Wark, Warren M. Farnworth, Mark E. Tuttle, Sidney B. Rigg, Steven D. Oliver, Kyle K. Kirby, Alan G. Wood, Lu Velicky
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Patent number: 8502353Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.Type: GrantFiled: June 7, 2011Date of Patent: August 6, 2013Assignee: Micron Technology, Inc.Inventors: Salman Akram, Charles M. Watkins, William M. Hiatt, David R. Hembree, James M. Wark, Warren M. Farnworth, Mark E. Tuttle, Sidney B. Rigg, Steven D. Oliver, Kyle K. Kirby, Alan G. Wood, Lu Velicky
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Patent number: 8324100Abstract: Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer.Type: GrantFiled: February 17, 2011Date of Patent: December 4, 2012Assignee: Micron Technology, Inc.Inventors: Salman Akram, William Mark Hiatt, Steven Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Patent number: 8294273Abstract: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.Type: GrantFiled: January 6, 2011Date of Patent: October 23, 2012Assignee: Micron Technology, Inc.Inventors: Salman Akram, William Mark Hiatt, Steve Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Patent number: 7993944Abstract: Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed herein. In one embodiment, the imager assembly can include a workpiece with a substrate having a front side, a back side, and a plurality of imaging dies on and/or in the substrate. The imaging dies include image sensors, integrated circuitry operatively coupled to the image sensors, and external contacts electrically coupled to the integrated circuitry. The assembly also includes optics supports on the workpiece. The optics supports have openings aligned with corresponding image sensors and first interface features at reference locations relative to corresponding image sensors. The assembly further includes optical devices having optics elements and second interface features seated with corresponding first interface features to position the optics elements at a desired location relative to corresponding image sensors.Type: GrantFiled: August 22, 2008Date of Patent: August 9, 2011Assignee: Micron Technology, Inc.Inventors: Steven D. Oliver, James M. Wark, Kyle K. Kirby
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Publication number: 20110136336Abstract: Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer.Type: ApplicationFiled: February 17, 2011Publication date: June 9, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Salman Akram, William Mark Hiatt, Steven Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Patent number: 7956443Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.Type: GrantFiled: March 17, 2010Date of Patent: June 7, 2011Assignee: Micron Technology, Inc.Inventors: Salman Akram, Charles M. Watkins, Mark Hiatt, David R. Hembree, James M. Wark, Warren M. Farnworth, Mark E. Tuttle, Sidney B. Rigg, Steven D. Oliver, Kyle K. Kirby, Alan G. Wood, Lu Velicky
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Publication number: 20110095429Abstract: Methods for forming conductive vias include foiling one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof A barrier layer may be fowled over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.Type: ApplicationFiled: January 6, 2011Publication date: April 28, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Salman Akram, William Mark Hiatt, Steve Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Patent number: 7928579Abstract: Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. The vias are formed within the substrate to have a longitudinal axis sloped at an angle with respect to a reference line extending perpendicular to the first surface and the second surface of the substrate. The vias may be formed from the first surface to the opposing second surface, or the via may be formed as a first blind opening from the first surface, then a second opening may be formed from the second surface to be aligned with the first opening. Vias may be formed completely through a first substrate and a second substrate, and the substrates may be bonded together. Semiconductor devices including the vias of the present invention are also disclosed. A method of forming spring-like contacts is also disclosed.Type: GrantFiled: October 27, 2006Date of Patent: April 19, 2011Assignee: Micron Technology, Inc.Inventors: James M. Wark, Syed S. Ahmad
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Patent number: 7892972Abstract: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.Type: GrantFiled: February 3, 2006Date of Patent: February 22, 2011Assignee: Micron Technology, Inc.Inventors: Salman Akram, William Mark Hiatt, Steve Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Patent number: 7855454Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: February 5, 2007Date of Patent: December 21, 2010Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William M. Hiatt
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Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
Patent number: 7812436Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and ten wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.Type: GrantFiled: August 25, 2008Date of Patent: October 12, 2010Assignee: Micron Technology, Inc.Inventor: James M. Wark